From c042fcc0c841df1fac357488798bcf919662b532 Mon Sep 17 00:00:00 2001
From: apan64 <andrew.pan@students.olin.edu>
Date: Sun, 10 Sep 2017 14:17:43 -0400
Subject: [PATCH] submitting hw1

---
 hw1.t.v     | 24 ++++++++++++++++++++++++
 hw1.v       | 26 ++++++++++++++++++++++++++
 results.txt |  5 +++++
 3 files changed, 55 insertions(+)
 create mode 100644 hw1.t.v
 create mode 100644 hw1.v
 create mode 100644 results.txt

diff --git a/hw1.t.v b/hw1.t.v
new file mode 100644
index 0000000..5aed625
--- /dev/null
+++ b/hw1.t.v
@@ -0,0 +1,24 @@
+`include "hw1.v"
+
+module demorgan_test ();
+
+  // Instantiate device/module under test
+  reg A, B;                // Primary test inputs
+  wire nA, nB, nAandnB, AandB, nAandB, nAornB, AorB, nAorB;    // Test outputs
+
+  demorgan dut(A, B, nA, nB, nAandnB, AandB, nAandB, nAornB, AorB, nAorB);  // Module to be tested
+
+
+  // Run sequence of test stimuli
+  initial begin
+    $display("A B | ~A ~B | ~A~B | AB | ~(AB) | ~A+~B | A+B | ~(A+B) ");            // Prints header for truth table
+    A=0;B=0; #1                                 // Set A and B, wait for update (#1)
+    $display("%b %b |  %b  %b |    %b |  %b |     %b |     %b |   %b |      %b ", A,B, nA, nB, nAandnB, AandB, nAandB, nAornB, AorB, nAorB);
+    A=0;B=1; #1                                 // Set A and B, wait for new update
+    $display("%b %b |  %b  %b |    %b |  %b |     %b |     %b |   %b |      %b ", A,B, nA, nB, nAandnB, AandB, nAandB, nAornB, AorB, nAorB);
+    A=1;B=0; #1
+    $display("%b %b |  %b  %b |    %b |  %b |     %b |     %b |   %b |      %b ", A,B, nA, nB, nAandnB, AandB, nAandB, nAornB, AorB, nAorB);
+    A=1;B=1; #1
+    $display("%b %b |  %b  %b |    %b |  %b |     %b |     %b |   %b |      %b ", A,B, nA, nB, nAandnB, AandB, nAandB, nAornB, AorB, nAorB);
+  end
+endmodule    // End demorgan_test
\ No newline at end of file
diff --git a/hw1.v b/hw1.v
new file mode 100644
index 0000000..552ff6c
--- /dev/null
+++ b/hw1.v
@@ -0,0 +1,26 @@
+module demorgan
+(
+  input  A,          // Single bit inputs
+  input  B,
+  output nA,         // Output intermediate complemented inputs
+  output nB,
+  output nAandnB,     // Single bit output, (~A)*(~B)
+  output AandB,        // intermediate A*B
+  output nAandB,       // ~(A*B)
+  output nAornB,      // ~A+~B
+  output AorB,        // intermediate A+B
+  output nAorB        // ~(A+B)
+);
+
+  wire nA;
+  wire nB;
+  not Ainv(nA, A);  	// Top inverter is named Ainv, takes signal A as input and produces signal nA
+  not Binv(nB, B);
+  and andgate(nAandnB, nA, nB); 	// AND gate produces nAandnB from nA and nB
+  and andgate2(AandB, A, B);
+  not AandBinv(nAandB, AandB);
+  or orgate1(nAornB, nA, nB);
+  or orgate2(AorB, A, B);
+  not AorBinv(nAorB, AorB);
+
+endmodule
\ No newline at end of file
diff --git a/results.txt b/results.txt
new file mode 100644
index 0000000..5466423
--- /dev/null
+++ b/results.txt
@@ -0,0 +1,5 @@
+A B | ~A ~B | ~A~B | AB | ~(AB) | ~A+~B | A+B | ~(A+B) 
+0 0 |  1  1 |    1 |  0 |     1 |     1 |   0 |      1 
+0 1 |  1  0 |    0 |  0 |     1 |     1 |   1 |      0 
+1 0 |  0  1 |    0 |  0 |     1 |     1 |   1 |      0 
+1 1 |  0  0 |    0 |  1 |     0 |     0 |   1 |      0