diff --git a/Write Up HW2.pdf b/Write Up HW2.pdf
new file mode 100644
index 0000000..fad41a2
Binary files /dev/null and b/Write Up HW2.pdf differ
diff --git a/adder.t.v b/adder.t.v
index 76109ed..3025ada 100644
--- a/adder.t.v
+++ b/adder.t.v
@@ -6,9 +6,29 @@ module testFullAdder();
     reg a, b, carryin;
     wire sum, carryout;
 
-    behavioralFullAdder adder (sum, carryout, a, b, carryin);
+    //behavioralFullAdder adder (sum, carryout, a, b, carryin);
+	structuralFullAdder adder (sum, carryout, a, b, carryin);
 
     initial begin
-        // Your test code here
+	$dumpfile("adder.vcd");
+	$dumpvars;
+
+    $display("A B CIn | Sum COut | Expected Output");
+    a=0; b=0; carryin=0; #1000
+    $display("%b  %b  %b | %b	%b  | 0 0", a, b, carryin, sum, carryout);
+    a=0; b=0; carryin=1; #1000
+    $display("%b  %b  %b | %b	%b  | 1 0", a, b, carryin, sum, carryout);
+    a=0; b=1; carryin=0; #1000
+    $display("%b  %b  %b | %b 	%b  | 1 0", a, b, carryin, sum, carryout);
+    a=0; b=1; carryin=1; #1000
+    $display("%b  %b  %b | %b 	%b  | 0 1", a, b, carryin, sum, carryout);
+    a=1; b=0; carryin=0; #1000
+    $display("%b  %b  %b | %b 	%b  | 1 0", a, b, carryin, sum, carryout);
+    a=1; b=0; carryin=1; #1000
+    $display("%b  %b  %b | %b 	%b  | 0 1", a, b, carryin, sum, carryout);
+    a=1; b=1; carryin=0; #1000
+    $display("%b  %b  %b | %b 	%b  | 0 1", a, b, carryin, sum, carryout);
+    a=1; b=1; carryin=1; #1000
+    $display("%b  %b  %b | %b 	%b  | 1 1", a, b, carryin, sum, carryout);
     end
 endmodule
diff --git a/adder.v b/adder.v
index d21f7e4..d7c8787 100644
--- a/adder.v
+++ b/adder.v
@@ -1,3 +1,7 @@
+`define AND and #50
+`define OR or #50
+`define XOR xor #50
+
 // Adder circuit
 
 module behavioralFullAdder
@@ -20,5 +24,15 @@ module structuralFullAdder
     input b, 
     input carryin
 );
-    // Your adder code here
+
+    wire AxorB;
+	wire AandB;
+	wire AxorBandCarryIn;
+	
+	`XOR (AxorB, a, b);
+	`XOR (sum, AxorB, carryin);
+	`AND (AandB, a, b);
+	`AND (AxorBandCarryIn, AxorB, carryin);
+	`OR (carryout, AxorBandCarryIn, AandB);
+	
 endmodule
diff --git a/decoder.t.v b/decoder.t.v
index e0e925f..9199081 100644
--- a/decoder.t.v
+++ b/decoder.t.v
@@ -7,10 +7,13 @@ module testDecoder ();
     reg enable;
     wire out0,out1,out2,out3;
 
-    behavioralDecoder decoder (out0,out1,out2,out3,addr0,addr1,enable);
-    //structuralDecoder decoder (out0,out1,out2,out3,addr0,addr1,enable); // Swap after testing
+    //behavioralDecoder decoder (out0,out1,out2,out3,addr0,addr1,enable);
+    structuralDecoder decoder (out0,out1,out2,out3,addr0,addr1,enable); // Swap after testing
 
     initial begin
+	$dumpfile("decoder.vcd");
+	$dumpvars;
+
     $display("En A0 A1| O0 O1 O2 O3 | Expected Output");
     enable=0;addr0=0;addr1=0; #1000 
     $display("%b  %b  %b |  %b  %b  %b  %b | All false", enable, addr0, addr1, out0, out1, out2, out3);
diff --git a/decoder.v b/decoder.v
index 17836e0..06facc2 100644
--- a/decoder.v
+++ b/decoder.v
@@ -1,3 +1,6 @@
+`define AND and #50
+`define NOT not #50
+
 // Decoder circuit
 
 module behavioralDecoder
@@ -17,6 +20,16 @@ module structuralDecoder
     input address0, address1,
     input enable
 );
-    // Your decoder code here
+
+	wire nA;
+	wire nB;
+	
+	`NOT (nA, address0);
+	`NOT (nB, address1);
+	`AND (out0, nA, nB, enable);
+	`AND (out1, address0, nB, enable);
+	`AND (out2, nA, address1, enable);
+	`AND (out3, address0, address1, enable);
+
 endmodule
 
diff --git a/multiplexer.t.v b/multiplexer.t.v
index fd475c4..35f3495 100644
--- a/multiplexer.t.v
+++ b/multiplexer.t.v
@@ -3,5 +3,34 @@
 `include "multiplexer.v"
 
 module testMultiplexer ();
-  // Your test code here
+    wire out;
+    reg address0, address1;
+    reg in0, in1, in2, in3;
+
+    //behavioralMultiplexer multiplexer (out, address0, address1, in0, in1, in2, in3);
+	structuralMultiplexer multiplexer (out, address0, address1, in0, in1, in2, in3);
+
+    initial begin
+	$dumpfile("multiplexer.vcd");
+	$dumpvars;
+
+    $display("A0 A1 |  In0 In1 In2 In3 | Out | Expected Output");
+    address0=0; address1=0; in0=0; in1=0; in2=0; in3=0; #1000
+    $display("%b  %b  |   %b  %b  %b  %b     |  %b  | 0", address0, address1, in0, in1, in2, in3, out);
+    address0=0; address1=0; in0=1; in1=0; in2=0; in3=0; #1000
+    $display("%b  %b  |   %b  %b  %b  %b     |  %b  | 1", address0, address1, in0, in1, in2, in3, out);
+    address0=0; address1=1; in0=0; in1=0; in2=0; in3=0; #1000
+    $display("%b  %b  |   %b  %b  %b  %b     |  %b  | 0", address0, address1, in0, in1, in2, in3, out);
+    address0=0; address1=1; in0=0; in1=0; in2=1; in3=0; #1000
+    $display("%b  %b  |   %b  %b  %b  %b     |  %b  | 1", address0, address1, in0, in1, in2, in3, out);
+    address0=1; address1=0; in0=0; in1=0; in2=0; in3=0; #1000
+    $display("%b  %b  |   %b  %b  %b  %b     |  %b  | 0", address0, address1, in0, in1, in2, in3, out);
+    address0=1; address1=0; in0=0; in1=1; in2=0; in3=0; #1000
+    $display("%b  %b  |   %b  %b  %b  %b     |  %b  | 1", address0, address1, in0, in1, in2, in3, out);
+    address0=1; address1=1; in0=0; in1=0; in2=0; in3=0; #1000
+    $display("%b  %b  |   %b  %b  %b  %b     |  %b  | 0", address0, address1, in0, in1, in2, in3, out);
+    address0=1; address1=1; in0=0; in1=0; in2=0; in3=1; #1000
+    $display("%b  %b  |   %b  %b  %b  %b     |  %b  | 1", address0, address1, in0, in1, in2, in3, out);
+    end
+  
 endmodule
diff --git a/multiplexer.v b/multiplexer.v
index b05820f..832114b 100644
--- a/multiplexer.v
+++ b/multiplexer.v
@@ -1,3 +1,7 @@
+`define AND and #50
+`define OR or #50
+`define NOT not #50
+
 // Multiplexer circuit
 
 module behavioralMultiplexer
@@ -19,6 +23,20 @@ module structuralMultiplexer
     input address0, address1,
     input in0, in1, in2, in3
 );
-    // Your multiplexer code here
-endmodule
 
+	wire nA;
+	wire nB;
+	wire nAandnBandin0;
+	wire AandnBandin1;
+	wire nAandBandin2;
+	wire AandBandin3;
+	
+	`NOT (nA, address0);
+	`NOT (nB, address1);
+	`AND (nAandnBandin0, nA, nB, in0);
+	`AND (AandnBandin1, address0, nB, in1);
+	`AND (nAandBandin2, nA, address1, in2);
+	`AND (AandBandin3, address0, address1, in3);
+	`OR (out, nAandnBandin0, AandnBandin1, nAandBandin2, AandBandin3);
+
+endmodule
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