diff --git a/adder b/adder new file mode 100755 index 0000000..be678f2 --- /dev/null +++ b/adder @@ -0,0 +1,170 @@ +#! /usr/local/bin/vvp +:ivl_version "0.10.0 (devel)" "(s20150513)"; +:ivl_delay_selection "TYPICAL"; +:vpi_time_precision - 12; +:vpi_module "system"; +:vpi_module "vhdl_sys"; +:vpi_module "v2005_math"; +:vpi_module "va_math"; +S_0x1403770 .scope module, "behavioralFullAdder" "behavioralFullAdder" 2 3; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x7fa5783d5060 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +v0x1404ad0_0 .net *"_s10", 0 0, L_0x7fa5783d5060; 1 drivers +v0x1429a50_0 .net *"_s11", 1 0, L_0x142c410; 1 drivers +v0x1429b30_0 .net *"_s13", 1 0, L_0x142c620; 1 drivers +L_0x7fa5783d50a8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +v0x1429c20_0 .net *"_s16", 0 0, L_0x7fa5783d50a8; 1 drivers +v0x1429d00_0 .net *"_s17", 1 0, L_0x142c750; 1 drivers +v0x1429e30_0 .net *"_s3", 1 0, L_0x142c170; 1 drivers +L_0x7fa5783d5018 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +v0x1429f10_0 .net *"_s6", 0 0, L_0x7fa5783d5018; 1 drivers +v0x1429ff0_0 .net *"_s7", 1 0, L_0x142c290; 1 drivers +o0x7fa57841e198 .functor BUFZ 1, C4; HiZ drive +v0x142a0d0_0 .net "a", 0 0, o0x7fa57841e198; 0 drivers +o0x7fa57841e1c8 .functor BUFZ 1, C4; HiZ drive +v0x142a220_0 .net "b", 0 0, o0x7fa57841e1c8; 0 drivers +o0x7fa57841e1f8 .functor BUFZ 1, C4; HiZ drive +v0x142a2e0_0 .net "carryin", 0 0, o0x7fa57841e1f8; 0 drivers +v0x142a3a0_0 .net "carryout", 0 0, L_0x142bfe0; 1 drivers +v0x142a460_0 .net "sum", 0 0, L_0x142c080; 1 drivers +L_0x142bfe0 .part L_0x142c750, 1, 1; +L_0x142c080 .part L_0x142c750, 0, 1; +L_0x142c170 .concat [ 1 1 0 0], o0x7fa57841e198, L_0x7fa5783d5018; +L_0x142c290 .concat [ 1 1 0 0], o0x7fa57841e1c8, L_0x7fa5783d5060; +L_0x142c410 .arith/sum 2, L_0x142c170, L_0x142c290; +L_0x142c620 .concat [ 1 1 0 0], o0x7fa57841e1f8, L_0x7fa5783d50a8; +L_0x142c750 .arith/sum 2, L_0x142c410, L_0x142c620; +S_0x1404950 .scope module, "testFullAdder" "testFullAdder" 3 10; + .timescale -9 -12; +v0x142bb10_0 .var "a", 0 0; +v0x142bc00_0 .var "b", 0 0; +v0x142bd10_0 .var "carryin", 0 0; +v0x142be00_0 .net "carryout", 0 0, L_0x142cde0; 1 drivers +v0x142bea0_0 .net "sum", 0 0, L_0x142cb90; 1 drivers +S_0x142a5c0 .scope module, "dut" "structuralFullAdder" 3 14, 2 25 0, S_0x1404950; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x142cde0/d .functor OR 1, L_0x142c910, L_0x142cc90, C4<0>, C4<0>; +L_0x142cde0 .delay 1 (50000,50000,50000) L_0x142cde0/d; +v0x142b460_0 .net "a", 0 0, v0x142bb10_0; 1 drivers +v0x142b520_0 .net "b", 0 0, v0x142bc00_0; 1 drivers +v0x142b5f0_0 .net "c1", 0 0, L_0x142c910; 1 drivers +v0x142b6f0_0 .net "c2", 0 0, L_0x142cc90; 1 drivers +v0x142b7c0_0 .net "carryin", 0 0, v0x142bd10_0; 1 drivers +v0x142b8b0_0 .net "carryout", 0 0, L_0x142cde0; alias, 1 drivers +v0x142b950_0 .net "s1", 0 0, L_0x142c510; 1 drivers +v0x142ba40_0 .net "sum", 0 0, L_0x142cb90; alias, 1 drivers +S_0x142a7e0 .scope module, "a1" "myHalfAdder" 2 36, 2 15 0, S_0x142a5c0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x142c510/d .functor XOR 1, v0x142bb10_0, v0x142bc00_0, C4<0>, C4<0>; +L_0x142c510 .delay 1 (50000,50000,50000) L_0x142c510/d; +L_0x142c910/d .functor AND 1, v0x142bb10_0, v0x142bc00_0, C4<1>, C4<1>; +L_0x142c910 .delay 1 (50000,50000,50000) L_0x142c910/d; +v0x142aa70_0 .net "a", 0 0, v0x142bb10_0; alias, 1 drivers +v0x142ab50_0 .net "b", 0 0, v0x142bc00_0; alias, 1 drivers +v0x142ac10_0 .net "carryout", 0 0, L_0x142c910; alias, 1 drivers +v0x142ace0_0 .net "sum", 0 0, L_0x142c510; alias, 1 drivers +S_0x142ae50 .scope module, "a2" "myHalfAdder" 2 37, 2 15 0, S_0x142a5c0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x142cb90/d .functor XOR 1, L_0x142c510, v0x142bd10_0, C4<0>, C4<0>; +L_0x142cb90 .delay 1 (50000,50000,50000) L_0x142cb90/d; +L_0x142cc90/d .functor AND 1, L_0x142c510, v0x142bd10_0, C4<1>, C4<1>; +L_0x142cc90 .delay 1 (50000,50000,50000) L_0x142cc90/d; +v0x142b0b0_0 .net "a", 0 0, L_0x142c510; alias, 1 drivers +v0x142b180_0 .net "b", 0 0, v0x142bd10_0; alias, 1 drivers +v0x142b220_0 .net "carryout", 0 0, L_0x142cc90; alias, 1 drivers +v0x142b2f0_0 .net "sum", 0 0, L_0x142cb90; alias, 1 drivers + .scope S_0x1404950; +T_0 ; + %vpi_call 3 17 "$dumpfile", "adder.vcd" {0 0 0}; + %vpi_call 3 18 "$dumpvars", 32'sb00000000000000000000000000000000, S_0x1404950 {0 0 0}; + %vpi_call 3 19 "$display", "a | b | carryin | carryout | carryout expected | sum | sum expected | " {0 0 0}; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x142bb10_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x142bc00_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x142bd10_0, 0, 1; + %delay 200000, 0; + %vpi_call 3 21 "$display", "%b | %b | %b | %b | %s | %b | %s | ", v0x142bb10_0, v0x142bc00_0, v0x142bd10_0, v0x142be00_0, "0", v0x142bea0_0, "0" {0 0 0}; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x142bb10_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x142bc00_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x142bd10_0, 0, 1; + %delay 200000, 0; + %vpi_call 3 23 "$display", "%b | %b | %b | %b | %s | %b | %s | ", v0x142bb10_0, v0x142bc00_0, v0x142bd10_0, v0x142be00_0, "0", v0x142bea0_0, "1" {0 0 0}; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x142bb10_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x142bc00_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x142bd10_0, 0, 1; + %delay 200000, 0; + %vpi_call 3 25 "$display", "%b | %b | %b | %b | %s | %b | %s | ", v0x142bb10_0, v0x142bc00_0, v0x142bd10_0, v0x142be00_0, "0", v0x142bea0_0, "1" {0 0 0}; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x142bb10_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x142bc00_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x142bd10_0, 0, 1; + %delay 200000, 0; + %vpi_call 3 27 "$display", "%b | %b | %b | %b | %s | %b | %s | ", v0x142bb10_0, v0x142bc00_0, v0x142bd10_0, v0x142be00_0, "1", v0x142bea0_0, "0" {0 0 0}; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x142bb10_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x142bc00_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x142bd10_0, 0, 1; + %delay 200000, 0; + %vpi_call 3 29 "$display", "%b | %b | %b | %b | %s | %b | %s | ", v0x142bb10_0, v0x142bc00_0, v0x142bd10_0, v0x142be00_0, "0", v0x142bea0_0, "1" {0 0 0}; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x142bb10_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x142bc00_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x142bd10_0, 0, 1; + %delay 200000, 0; + %vpi_call 3 31 "$display", "%b | %b | %b | %b | %s | %b | %s | ", v0x142bb10_0, v0x142bc00_0, v0x142bd10_0, v0x142be00_0, "1", v0x142bea0_0, "0" {0 0 0}; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x142bb10_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x142bc00_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x142bd10_0, 0, 1; + %delay 200000, 0; + %vpi_call 3 33 "$display", "%b | %b | %b | %b | %s | %b | %s | ", v0x142bb10_0, v0x142bc00_0, v0x142bd10_0, v0x142be00_0, "1", v0x142bea0_0, "0" {0 0 0}; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x142bb10_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x142bc00_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x142bd10_0, 0, 1; + %delay 200000, 0; + %vpi_call 3 35 "$display", "%b | %b | %b | %b | %s | %b | %s | ", v0x142bb10_0, v0x142bc00_0, v0x142bd10_0, v0x142be00_0, "1", v0x142bea0_0, "1" {0 0 0}; + %end; + .thread T_0; +# The file index is used to find the file name in the following table. +:file_names 4; + "N/A"; + ""; + "./adder.v"; + "adder.t.v"; diff --git a/adder.t.v b/adder.t.v index 76109ed..fe981c2 100644 --- a/adder.t.v +++ b/adder.t.v @@ -1,3 +1,8 @@ +// define gates with delays +`define AND and #50 +`define OR or #50 +`define XOR xor #50 + // Adder testbench `timescale 1 ns / 1 ps `include "adder.v" @@ -6,9 +11,27 @@ module testFullAdder(); reg a, b, carryin; wire sum, carryout; - behavioralFullAdder adder (sum, carryout, a, b, carryin); + structuralFullAdder dut(sum, carryout, a, b, carryin); initial begin - // Your test code here + $dumpfile("adder.vcd"); + $dumpvars(0, testFullAdder); + $display("a | b | carryin | carryout | carryout expected | sum | sum expected | "); + a=0;b=0;carryin=0;#200 + $display("%b | %b | %b | %b | %s | %b | %s | ", a, b, carryin, carryout, "0", sum, "0"); + a=0;b=0;carryin=1;#200 + $display("%b | %b | %b | %b | %s | %b | %s | ", a, b, carryin, carryout, "0", sum, "1"); + a=0;b=1;carryin=0;#200 + $display("%b | %b | %b | %b | %s | %b | %s | ", a, b, carryin, carryout, "0", sum, "1"); + a=0;b=1;carryin=1;#200 + $display("%b | %b | %b | %b | %s | %b | %s | ", a, b, carryin, carryout, "1", sum, "0"); + a=1;b=0;carryin=0;#200 + $display("%b | %b | %b | %b | %s | %b | %s | ", a, b, carryin, carryout, "0", sum, "1"); + a=1;b=0;carryin=1;#200 + $display("%b | %b | %b | %b | %s | %b | %s | ", a, b, carryin, carryout, "1", sum, "0"); + a=1;b=1;carryin=0;#200 + $display("%b | %b | %b | %b | %s | %b | %s | ", a, b, carryin, carryout, "1", sum, "0"); + a=1;b=1;carryin=1;#200 + $display("%b | %b | %b | %b | %s | %b | %s | ", a, b, carryin, carryout, "1", sum, "1"); end endmodule diff --git a/adder.v b/adder.v index d21f7e4..2c58370 100644 --- a/adder.v +++ b/adder.v @@ -2,23 +2,38 @@ module behavioralFullAdder ( - output sum, + output sum, output carryout, - input a, - input b, + input a, + input b, input carryin ); // Uses concatenation operator and built-in '+' assign {carryout, sum}=a+b+carryin; endmodule +module myHalfAdder( + output sum, + output carryout, + input a, + input b +); + `XOR axorb(sum,a,b); + `AND aandb(carryout,a,b); +endmodule + module structuralFullAdder ( - output sum, + output sum, output carryout, - input a, - input b, + input a, + input b, input carryin ); - // Your adder code here + wire s1; + wire c1; + wire c2; + myHalfAdder a1(s1,c1,a,b); + myHalfAdder a2(sum, c2, s1, carryin); + `OR (carryout, c1, c2); endmodule diff --git a/adder.vcd b/adder.vcd new file mode 100644 index 0000000..5c08dad --- /dev/null +++ b/adder.vcd @@ -0,0 +1,107 @@ +$date + Thu Sep 21 20:51:58 2017 +$end +$version + Icarus Verilog +$end +$timescale + 1ps +$end +$scope module testFullAdder $end +$var wire 1 ! sum $end +$var wire 1 " carryout $end +$var reg 1 # a $end +$var reg 1 $ b $end +$var reg 1 % carryin $end +$scope module dut $end +$var wire 1 # a $end +$var wire 1 $ b $end +$var wire 1 % carryin $end +$var wire 1 " carryout $end +$var wire 1 ! sum $end +$var wire 1 & s1 $end +$var wire 1 ' c2 $end +$var wire 1 ( c1 $end +$scope module a1 $end +$var wire 1 # a $end +$var wire 1 $ b $end +$var wire 1 ( carryout $end +$var wire 1 & sum $end +$upscope $end +$scope module a2 $end +$var wire 1 & a $end +$var wire 1 % b $end +$var wire 1 ' carryout $end +$var wire 1 ! sum $end +$upscope $end +$upscope $end +$upscope $end +$enddefinitions $end +#0 +$dumpvars +x( +x' +x& +0% +0$ +0# +x" +x! +$end +#50000 +0' +0( +0& +#100000 +0" +0! +#200000 +1% +#250000 +1! +#400000 +0% +1$ +#450000 +0! +1& +#500000 +1! +#600000 +1% +#650000 +0! +1' +#700000 +1" +#800000 +0% +0$ +1# +#850000 +1! +0' +#900000 +0" +#1000000 +1% +#1050000 +0! +1' +#1100000 +1" +#1200000 +0% +1$ +#1250000 +1! +0' +0& +1( +#1300000 +0! +#1400000 +1% +#1450000 +1! +#1600000 diff --git a/adderTable.txt b/adderTable.txt new file mode 100644 index 0000000..0ca631d --- /dev/null +++ b/adderTable.txt @@ -0,0 +1,10 @@ +VCD info: dumpfile adder.vcd opened for output. +a | b | carryin | carryout | carryout expected | sum | sum expected | +0 | 0 | 0 | 0 | 0 | 0 | 0 | +0 | 0 | 1 | 0 | 0 | 1 | 1 | +0 | 1 | 0 | 0 | 0 | 1 | 1 | +0 | 1 | 1 | 1 | 1 | 0 | 0 | +1 | 0 | 0 | 0 | 0 | 1 | 1 | +1 | 0 | 1 | 1 | 1 | 0 | 0 | +1 | 1 | 0 | 1 | 1 | 0 | 0 | +1 | 1 | 1 | 1 | 1 | 1 | 1 | diff --git a/adderTrace.png b/adderTrace.png new file mode 100644 index 0000000..8822a89 Binary files /dev/null and b/adderTrace.png differ diff --git a/decoder b/decoder new file mode 100755 index 0000000..97caac7 --- /dev/null +++ b/decoder @@ -0,0 +1,194 @@ +#! /usr/local/bin/vvp +:ivl_version "0.10.0 (devel)" "(s20150513)"; +:ivl_delay_selection "TYPICAL"; +:vpi_time_precision - 12; +:vpi_module "system"; +:vpi_module "vhdl_sys"; +:vpi_module "v2005_math"; +:vpi_module "va_math"; +S_0x23694d0 .scope module, "behavioralDecoder" "behavioralDecoder" 2 3; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out0" + .port_info 1 /OUTPUT 1 "out1" + .port_info 2 /OUTPUT 1 "out2" + .port_info 3 /OUTPUT 1 "out3" + .port_info 4 /INPUT 1 "address0" + .port_info 5 /INPUT 1 "address1" + .port_info 6 /INPUT 1 "enable" +v0x23700b0_0 .net *"_s11", 3 0, L_0x2397b00; 1 drivers +v0x23945a0_0 .net *"_s5", 3 0, L_0x2397950; 1 drivers +L_0x7fc33c3f5018 .functor BUFT 1, C4<000>, C4<0>, C4<0>, C4<0>; +v0x2394680_0 .net *"_s8", 2 0, L_0x7fc33c3f5018; 1 drivers +v0x2394770_0 .net *"_s9", 1 0, L_0x23979f0; 1 drivers +o0x7fc33c43e0d8 .functor BUFZ 1, C4; HiZ drive +v0x2394850_0 .net "address0", 0 0, o0x7fc33c43e0d8; 0 drivers +o0x7fc33c43e108 .functor BUFZ 1, C4; HiZ drive +v0x2394960_0 .net "address1", 0 0, o0x7fc33c43e108; 0 drivers +o0x7fc33c43e138 .functor BUFZ 1, C4; HiZ drive +v0x2394a20_0 .net "enable", 0 0, o0x7fc33c43e138; 0 drivers +v0x2394ae0_0 .net "out0", 0 0, L_0x2397820; 1 drivers +v0x2394ba0_0 .net "out1", 0 0, L_0x2397780; 1 drivers +v0x2394cf0_0 .net "out2", 0 0, L_0x2397690; 1 drivers +v0x2394db0_0 .net "out3", 0 0, L_0x23975f0; 1 drivers +L_0x23975f0 .part L_0x2397b00, 3, 1; +L_0x2397690 .part L_0x2397b00, 2, 1; +L_0x2397780 .part L_0x2397b00, 1, 1; +L_0x2397820 .part L_0x2397b00, 0, 1; +L_0x2397950 .concat [ 1 3 0 0], o0x7fc33c43e138, L_0x7fc33c3f5018; +L_0x23979f0 .concat [ 1 1 0 0], o0x7fc33c43e0d8, o0x7fc33c43e108; +L_0x2397b00 .shift/l 4, L_0x2397950, L_0x23979f0; +S_0x236ff30 .scope module, "testDecoder" "testDecoder" 3 9; + .timescale -9 -12; +v0x2396f40_0 .var "addr0", 0 0; +v0x2396fe0_0 .var "addr1", 0 0; +v0x23970f0_0 .var "enable", 0 0; +v0x23971e0_0 .net "out0", 0 0, L_0x2398150; 1 drivers +v0x23972d0_0 .net "out1", 0 0, L_0x2398340; 1 drivers +v0x2397410_0 .net "out2", 0 0, L_0x2398560; 1 drivers +v0x2397500_0 .net "out3", 0 0, L_0x23986b0; 1 drivers +S_0x2394f90 .scope module, "decoder" "structuralDecoder" 3 15, 2 25 0, S_0x236ff30; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out0" + .port_info 1 /OUTPUT 1 "out1" + .port_info 2 /OUTPUT 1 "out2" + .port_info 3 /OUTPUT 1 "out3" + .port_info 4 /INPUT 1 "address0" + .port_info 5 /INPUT 1 "address1" + .port_info 6 /INPUT 1 "enable" +v0x23966e0_0 .net "address0", 0 0, v0x2396f40_0; 1 drivers +v0x23967f0_0 .net "address1", 0 0, v0x2396fe0_0; 1 drivers +v0x23968b0_0 .net "enable", 0 0, v0x23970f0_0; 1 drivers +v0x2396980_0 .net "out0", 0 0, L_0x2398150; alias, 1 drivers +v0x2396a50_0 .net "out1", 0 0, L_0x2398340; alias, 1 drivers +v0x2396b40_0 .net "out2", 0 0, L_0x2398560; alias, 1 drivers +v0x2396c10_0 .net "out3", 0 0, L_0x23986b0; alias, 1 drivers +v0x2396ce0_0 .net "w0", 0 0, L_0x2397d00; 1 drivers +v0x2396dd0_0 .net "w1", 0 0, L_0x2397e60; 1 drivers +S_0x23951e0 .scope module, "d1" "oneBitDecoder" 2 32, 2 14 0, S_0x2394f90; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out0" + .port_info 1 /OUTPUT 1 "out1" + .port_info 2 /INPUT 1 "address" + .port_info 3 /INPUT 1 "enable" +L_0x2397c40/d .functor NOT 1, v0x2396fe0_0, C4<0>, C4<0>, C4<0>; +L_0x2397c40 .delay 1 (50000,50000,50000) L_0x2397c40/d; +L_0x2397d00/d .functor AND 1, L_0x2397c40, v0x23970f0_0, C4<1>, C4<1>; +L_0x2397d00 .delay 1 (50000,50000,50000) L_0x2397d00/d; +L_0x2397e60/d .functor AND 1, v0x2396fe0_0, v0x23970f0_0, C4<1>, C4<1>; +L_0x2397e60 .delay 1 (50000,50000,50000) L_0x2397e60/d; +v0x2395440_0 .net "_address", 0 0, L_0x2397c40; 1 drivers +v0x2395520_0 .net "address", 0 0, v0x2396fe0_0; alias, 1 drivers +v0x23955e0_0 .net "enable", 0 0, v0x23970f0_0; alias, 1 drivers +v0x23956b0_0 .net "out0", 0 0, L_0x2397d00; alias, 1 drivers +v0x2395770_0 .net "out1", 0 0, L_0x2397e60; alias, 1 drivers +S_0x2395900 .scope module, "d2" "oneBitDecoder" 2 33, 2 14 0, S_0x2394f90; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out0" + .port_info 1 /OUTPUT 1 "out1" + .port_info 2 /INPUT 1 "address" + .port_info 3 /INPUT 1 "enable" +L_0x2398050/d .functor NOT 1, v0x2396f40_0, C4<0>, C4<0>, C4<0>; +L_0x2398050 .delay 1 (50000,50000,50000) L_0x2398050/d; +L_0x2398150/d .functor AND 1, L_0x2398050, L_0x2397d00, C4<1>, C4<1>; +L_0x2398150 .delay 1 (50000,50000,50000) L_0x2398150/d; +L_0x2398340/d .functor AND 1, v0x2396f40_0, L_0x2397d00, C4<1>, C4<1>; +L_0x2398340 .delay 1 (50000,50000,50000) L_0x2398340/d; +v0x2395b60_0 .net "_address", 0 0, L_0x2398050; 1 drivers +v0x2395c20_0 .net "address", 0 0, v0x2396f40_0; alias, 1 drivers +v0x2395ce0_0 .net "enable", 0 0, L_0x2397d00; alias, 1 drivers +v0x2395de0_0 .net "out0", 0 0, L_0x2398150; alias, 1 drivers +v0x2395e80_0 .net "out1", 0 0, L_0x2398340; alias, 1 drivers +S_0x2395ff0 .scope module, "d3" "oneBitDecoder" 2 34, 2 14 0, S_0x2394f90; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out0" + .port_info 1 /OUTPUT 1 "out1" + .port_info 2 /INPUT 1 "address" + .port_info 3 /INPUT 1 "enable" +L_0x2398400/d .functor NOT 1, v0x2396f40_0, C4<0>, C4<0>, C4<0>; +L_0x2398400 .delay 1 (50000,50000,50000) L_0x2398400/d; +L_0x2398560/d .functor AND 1, L_0x2398400, L_0x2397e60, C4<1>, C4<1>; +L_0x2398560 .delay 1 (50000,50000,50000) L_0x2398560/d; +L_0x23986b0/d .functor AND 1, v0x2396f40_0, L_0x2397e60, C4<1>, C4<1>; +L_0x23986b0 .delay 1 (50000,50000,50000) L_0x23986b0/d; +v0x2396260_0 .net "_address", 0 0, L_0x2398400; 1 drivers +v0x2396320_0 .net "address", 0 0, v0x2396f40_0; alias, 1 drivers +v0x2396410_0 .net "enable", 0 0, L_0x2397e60; alias, 1 drivers +v0x2396510_0 .net "out0", 0 0, L_0x2398560; alias, 1 drivers +v0x23965b0_0 .net "out1", 0 0, L_0x23986b0; alias, 1 drivers + .scope S_0x236ff30; +T_0 ; + %vpi_call 3 18 "$dumpfile", "decoder.vcd" {0 0 0}; + %vpi_call 3 19 "$dumpvars", 32'sb00000000000000000000000000000000, S_0x236ff30 {0 0 0}; + %vpi_call 3 20 "$display", "En A0 A1| O0 O1 O2 O3 | Expected Output" {0 0 0}; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x23970f0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x2396f40_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x2396fe0_0, 0, 1; + %delay 1000000, 0; + %vpi_call 3 22 "$display", "%b %b %b | %b %b %b %b | All false", v0x23970f0_0, v0x2396f40_0, v0x2396fe0_0, v0x23971e0_0, v0x23972d0_0, v0x2397410_0, v0x2397500_0 {0 0 0}; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x23970f0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x2396f40_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x2396fe0_0, 0, 1; + %delay 1000000, 0; + %vpi_call 3 24 "$display", "%b %b %b | %b %b %b %b | All false", v0x23970f0_0, v0x2396f40_0, v0x2396fe0_0, v0x23971e0_0, v0x23972d0_0, v0x2397410_0, v0x2397500_0 {0 0 0}; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x23970f0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x2396f40_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x2396fe0_0, 0, 1; + %delay 1000000, 0; + %vpi_call 3 26 "$display", "%b %b %b | %b %b %b %b | All false", v0x23970f0_0, v0x2396f40_0, v0x2396fe0_0, v0x23971e0_0, v0x23972d0_0, v0x2397410_0, v0x2397500_0 {0 0 0}; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x23970f0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x2396f40_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x2396fe0_0, 0, 1; + %delay 1000000, 0; + %vpi_call 3 28 "$display", "%b %b %b | %b %b %b %b | All false", v0x23970f0_0, v0x2396f40_0, v0x2396fe0_0, v0x23971e0_0, v0x23972d0_0, v0x2397410_0, v0x2397500_0 {0 0 0}; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x23970f0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x2396f40_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x2396fe0_0, 0, 1; + %delay 1000000, 0; + %vpi_call 3 30 "$display", "%b %b %b | %b %b %b %b | O0 Only", v0x23970f0_0, v0x2396f40_0, v0x2396fe0_0, v0x23971e0_0, v0x23972d0_0, v0x2397410_0, v0x2397500_0 {0 0 0}; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x23970f0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x2396f40_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x2396fe0_0, 0, 1; + %delay 1000000, 0; + %vpi_call 3 32 "$display", "%b %b %b | %b %b %b %b | O1 Only", v0x23970f0_0, v0x2396f40_0, v0x2396fe0_0, v0x23971e0_0, v0x23972d0_0, v0x2397410_0, v0x2397500_0 {0 0 0}; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x23970f0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x2396f40_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x2396fe0_0, 0, 1; + %delay 1000000, 0; + %vpi_call 3 34 "$display", "%b %b %b | %b %b %b %b | O2 Only", v0x23970f0_0, v0x2396f40_0, v0x2396fe0_0, v0x23971e0_0, v0x23972d0_0, v0x2397410_0, v0x2397500_0 {0 0 0}; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x23970f0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x2396f40_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x2396fe0_0, 0, 1; + %delay 1000000, 0; + %vpi_call 3 36 "$display", "%b %b %b | %b %b %b %b | O3 Only", v0x23970f0_0, v0x2396f40_0, v0x2396fe0_0, v0x23971e0_0, v0x23972d0_0, v0x2397410_0, v0x2397500_0 {0 0 0}; + %end; + .thread T_0; +# The file index is used to find the file name in the following table. +:file_names 4; + "N/A"; + ""; + "./decoder.v"; + "decoder.t.v"; diff --git a/decoder.t.v b/decoder.t.v index e0e925f..f430cfd 100644 --- a/decoder.t.v +++ b/decoder.t.v @@ -1,32 +1,38 @@ // Decoder testbench +`define AND and #50 +`define OR or #50 +`define NOT not #50 + `timescale 1 ns / 1 ps `include "decoder.v" -module testDecoder (); +module testDecoder (); reg addr0, addr1; reg enable; wire out0,out1,out2,out3; - behavioralDecoder decoder (out0,out1,out2,out3,addr0,addr1,enable); - //structuralDecoder decoder (out0,out1,out2,out3,addr0,addr1,enable); // Swap after testing + //behavioralDecoder decoder (out0,out1,out2,out3,addr0,addr1,enable); + structuralDecoder decoder (out0,out1,out2,out3,addr0,addr1,enable); // Swap after testing initial begin + $dumpfile("decoder.vcd"); + $dumpvars(0, testDecoder); $display("En A0 A1| O0 O1 O2 O3 | Expected Output"); - enable=0;addr0=0;addr1=0; #1000 + enable=0;addr0=0;addr1=0; #1000 $display("%b %b %b | %b %b %b %b | All false", enable, addr0, addr1, out0, out1, out2, out3); enable=0;addr0=1;addr1=0; #1000 $display("%b %b %b | %b %b %b %b | All false", enable, addr0, addr1, out0, out1, out2, out3); - enable=0;addr0=0;addr1=1; #1000 + enable=0;addr0=0;addr1=1; #1000 $display("%b %b %b | %b %b %b %b | All false", enable, addr0, addr1, out0, out1, out2, out3); - enable=0;addr0=1;addr1=1; #1000 + enable=0;addr0=1;addr1=1; #1000 $display("%b %b %b | %b %b %b %b | All false", enable, addr0, addr1, out0, out1, out2, out3); - enable=1;addr0=0;addr1=0; #1000 + enable=1;addr0=0;addr1=0; #1000 $display("%b %b %b | %b %b %b %b | O0 Only", enable, addr0, addr1, out0, out1, out2, out3); - enable=1;addr0=1;addr1=0; #1000 + enable=1;addr0=1;addr1=0; #1000 $display("%b %b %b | %b %b %b %b | O1 Only", enable, addr0, addr1, out0, out1, out2, out3); - enable=1;addr0=0;addr1=1; #1000 + enable=1;addr0=0;addr1=1; #1000 $display("%b %b %b | %b %b %b %b | O2 Only", enable, addr0, addr1, out0, out1, out2, out3); - enable=1;addr0=1;addr1=1; #1000 + enable=1;addr0=1;addr1=1; #1000 $display("%b %b %b | %b %b %b %b | O3 Only", enable, addr0, addr1, out0, out1, out2, out3); end diff --git a/decoder.v b/decoder.v index 17836e0..3e2447b 100644 --- a/decoder.v +++ b/decoder.v @@ -11,12 +11,25 @@ module behavioralDecoder endmodule +module oneBitDecoder( + output out0, out1, + input address, + input enable +); +wire _address; +`NOT nAd(_address, address); +`AND o0(out0, _address, enable); +`AND o1(out1, address, enable); +endmodule //#100 + module structuralDecoder ( output out0, out1, out2, out3, input address0, address1, input enable ); - // Your decoder code here + wire w0,w1; + oneBitDecoder d1(w0,w1,address1,enable); //#100 + oneBitDecoder d2(out0, out1, address0, w0); //#200 + oneBitDecoder d3(out2, out3, address0, w1); //#200 endmodule - diff --git a/decoder.vcd b/decoder.vcd new file mode 100644 index 0000000..9e8ab8d --- /dev/null +++ b/decoder.vcd @@ -0,0 +1,138 @@ +$date + Thu Sep 21 21:07:41 2017 +$end +$version + Icarus Verilog +$end +$timescale + 1ps +$end +$scope module testDecoder $end +$var wire 1 ! out3 $end +$var wire 1 " out2 $end +$var wire 1 # out1 $end +$var wire 1 $ out0 $end +$var reg 1 % addr0 $end +$var reg 1 & addr1 $end +$var reg 1 ' enable $end +$scope module decoder $end +$var wire 1 % address0 $end +$var wire 1 & address1 $end +$var wire 1 ' enable $end +$var wire 1 ( w1 $end +$var wire 1 ) w0 $end +$var wire 1 ! out3 $end +$var wire 1 " out2 $end +$var wire 1 # out1 $end +$var wire 1 $ out0 $end +$scope module d1 $end +$var wire 1 * _address $end +$var wire 1 & address $end +$var wire 1 ' enable $end +$var wire 1 ) out0 $end +$var wire 1 ( out1 $end +$upscope $end +$scope module d2 $end +$var wire 1 + _address $end +$var wire 1 % address $end +$var wire 1 ) enable $end +$var wire 1 $ out0 $end +$var wire 1 # out1 $end +$upscope $end +$scope module d3 $end +$var wire 1 , _address $end +$var wire 1 % address $end +$var wire 1 ( enable $end +$var wire 1 " out0 $end +$var wire 1 ! out1 $end +$upscope $end +$upscope $end +$upscope $end +$enddefinitions $end +#0 +$dumpvars +x, +x+ +x* +x) +x( +0' +0& +0% +x$ +x# +x" +x! +$end +#50000 +1* +1+ +1, +0! +0# +0( +0) +#100000 +0" +0$ +#1000000 +1% +#1050000 +0+ +0, +#2000000 +1& +0% +#2050000 +0* +1+ +1, +#3000000 +1% +#3050000 +0+ +0, +#4000000 +0& +0% +1' +#4050000 +1* +1+ +1, +#4100000 +1) +#4150000 +1$ +#5000000 +1% +#5050000 +0+ +1# +0, +#5100000 +0$ +#6000000 +1& +0% +#6050000 +0* +1( +1+ +0# +1, +#6100000 +0) +1$ +1" +#6150000 +0$ +#7000000 +1% +#7050000 +0+ +0, +1! +#7100000 +0" +#8000000 diff --git a/decoderTable.txt b/decoderTable.txt new file mode 100644 index 0000000..5dc4ebc --- /dev/null +++ b/decoderTable.txt @@ -0,0 +1,9 @@ +En A0 A1| O0 O1 O2 O3 | Expected Output +0 0 0 | 0 0 0 0 | All false +0 1 0 | 0 0 0 0 | All false +0 0 1 | 0 0 0 0 | All false +0 1 1 | 0 0 0 0 | All false +1 0 0 | 1 0 0 0 | O0 Only +1 1 0 | 0 1 0 0 | O1 Only +1 0 1 | 0 0 1 0 | O2 Only +1 1 1 | 0 0 0 1 | O3 Only diff --git a/decoderTrace.png b/decoderTrace.png new file mode 100644 index 0000000..787df73 Binary files /dev/null and b/decoderTrace.png differ diff --git a/makeTest.py b/makeTest.py new file mode 100644 index 0000000..a6c72c8 --- /dev/null +++ b/makeTest.py @@ -0,0 +1,66 @@ +from itertools import product + +def expected(*args): + args = args[0] + a0 = args[0]=='1' + a1 = args[1]=='1' + i0 = args[2]; + i1 = args[3]; + i2 = args[4]; + i3 = args[5]; + if not a1 and not a0: + return [i0] + if not a1 and a0: + return [i1] + if a1 and not a0: + return [i2] + if a1 and a0: + return [i3] + + +inputs = ("address0","address1","in0","in1","in2","in3") +outputs = ["out"] + +lengths = [] +delay = 1000; + +numInputs = len(inputs) +numOutputs = len(outputs) +print("$display(\"", end="") +for eachInput in inputs: + string = eachInput+" | " + lengths.append(len(string)) + print(string, end="") +for eachOutput in outputs: + string = eachOutput+" | " + lengths.append(len(string)) + print(string, end="") + string = eachOutput+" expected | " + lengths.append(len(string)) + print(string, end="") +print("\");") + +for inputVals in product("01",repeat=numInputs): + for i, eachInput in enumerate(inputs): + print(eachInput+"="+inputVals[i]+";",end="") + print("#"+str(delay)) + print("$display(\"", end="") + i = 0 + for eachInput in inputs: + print("%b"+" "*(lengths[i]-3)+"| ", end="") + i=i+1 + for eachOutput in outputs: + print("%b"+" "*(lengths[i]-3)+"| ", end="") + i=i+1 + print("%s"+" "*(lengths[i]-3)+"| ", end="") + i=i+1 + print("\", ", end="") + expectedOutputs = expected(inputVals) + for eachInput in inputs: + print(eachInput+", ", end="") + for i, eachOutput in enumerate(outputs): + print(eachOutput+", ", end="") + if i < numOutputs-1: + print("\""+expectedOutputs[i]+"\", ", end="") + else: + print("\""+expectedOutputs[i]+"\");") diff --git a/multiplexer.t.v b/multiplexer.t.v index fd475c4..e88341e 100644 --- a/multiplexer.t.v +++ b/multiplexer.t.v @@ -1,7 +1,147 @@ // Multiplexer testbench +`define AND and #50 +`define OR or #50 +`define NOT not #50 `timescale 1 ns / 1 ps `include "multiplexer.v" module testMultiplexer (); - // Your test code here + reg address0, address1; + reg in0, in1, in2, in3; + wire out; + + structuralMultiplexer dut(out, address0, address1, in0, in1, in2, in3); + initial begin + $dumpfile("mux.vcd"); + $dumpvars(0, testMultiplexer); + $display("address0 | address1 | in0 | in1 | in2 | in3 | out | out expected | "); + address0=0;address1=0;in0=0;in1=0;in2=0;in3=0;#1000 + $display("%b | %b | %b | %b | %b | %b | %b | %s | ", address0, address1, in0, in1, in2, in3, out, "0"); + address0=0;address1=0;in0=0;in1=0;in2=0;in3=1;#1000 + $display("%b | %b | %b | %b | %b | %b | %b | %s | ", address0, address1, in0, in1, in2, in3, out, "0"); + address0=0;address1=0;in0=0;in1=0;in2=1;in3=0;#1000 + $display("%b | %b | %b | %b | %b | %b | %b | %s | ", address0, address1, in0, in1, in2, in3, out, "0"); + address0=0;address1=0;in0=0;in1=0;in2=1;in3=1;#1000 + $display("%b | %b | %b | %b | %b | %b | %b | %s | ", address0, address1, in0, in1, in2, in3, out, "0"); + address0=0;address1=0;in0=0;in1=1;in2=0;in3=0;#1000 + $display("%b | %b | %b | %b | %b | %b | %b | %s | ", address0, address1, in0, in1, in2, in3, out, "0"); + address0=0;address1=0;in0=0;in1=1;in2=0;in3=1;#1000 + $display("%b | %b | %b | %b | %b | %b | %b | %s | ", address0, address1, in0, in1, in2, in3, out, "0"); + address0=0;address1=0;in0=0;in1=1;in2=1;in3=0;#1000 + $display("%b | %b | %b | %b | %b | %b | %b | %s | ", address0, address1, in0, in1, in2, in3, out, "0"); + address0=0;address1=0;in0=0;in1=1;in2=1;in3=1;#1000 + $display("%b | %b | %b | %b | %b | %b | %b | %s | ", address0, address1, in0, in1, in2, in3, out, "0"); + address0=0;address1=0;in0=1;in1=0;in2=0;in3=0;#1000 + $display("%b | %b | %b | %b | %b | %b | %b | %s | ", address0, address1, in0, in1, in2, in3, out, "1"); + address0=0;address1=0;in0=1;in1=0;in2=0;in3=1;#1000 + $display("%b | %b | %b | %b | %b | %b | %b | %s | ", address0, address1, in0, in1, in2, in3, out, "1"); + address0=0;address1=0;in0=1;in1=0;in2=1;in3=0;#1000 + $display("%b | %b | %b | %b | %b | %b | %b | %s | ", address0, address1, in0, in1, in2, in3, out, "1"); + address0=0;address1=0;in0=1;in1=0;in2=1;in3=1;#1000 + $display("%b | %b | %b | %b | %b | %b | %b | %s | ", address0, address1, in0, in1, in2, in3, out, "1"); + address0=0;address1=0;in0=1;in1=1;in2=0;in3=0;#1000 + $display("%b | %b | %b | %b | %b | %b | %b | %s | ", address0, address1, in0, in1, in2, in3, out, "1"); + address0=0;address1=0;in0=1;in1=1;in2=0;in3=1;#1000 + $display("%b | %b | %b | %b | %b | %b | %b | %s | ", address0, address1, in0, in1, in2, in3, out, "1"); + address0=0;address1=0;in0=1;in1=1;in2=1;in3=0;#1000 + $display("%b | %b | %b | %b | %b | %b | %b | %s | ", address0, address1, in0, in1, in2, in3, out, "1"); + address0=0;address1=0;in0=1;in1=1;in2=1;in3=1;#1000 + $display("%b | %b | %b | %b | %b | %b | %b | %s | ", address0, address1, in0, in1, in2, in3, out, "1"); + address0=0;address1=1;in0=0;in1=0;in2=0;in3=0;#1000 + $display("%b | %b | %b | %b | %b | %b | %b | %s | ", address0, address1, in0, in1, in2, in3, out, "0"); + address0=0;address1=1;in0=0;in1=0;in2=0;in3=1;#1000 + $display("%b | %b | %b | %b | %b | %b | %b | %s | ", address0, address1, in0, in1, in2, in3, out, "0"); + address0=0;address1=1;in0=0;in1=0;in2=1;in3=0;#1000 + $display("%b | %b | %b | %b | %b | %b | %b | %s | ", address0, address1, in0, in1, in2, in3, out, "1"); + address0=0;address1=1;in0=0;in1=0;in2=1;in3=1;#1000 + $display("%b | %b | %b | %b | %b | %b | %b | %s | ", address0, address1, in0, in1, in2, in3, out, "1"); + address0=0;address1=1;in0=0;in1=1;in2=0;in3=0;#1000 + $display("%b | %b | %b | %b | %b | %b | %b | %s | ", address0, address1, in0, in1, in2, in3, out, "0"); + address0=0;address1=1;in0=0;in1=1;in2=0;in3=1;#1000 + $display("%b | %b | %b | %b | %b | %b | %b | %s | ", address0, address1, in0, in1, in2, in3, out, "0"); + address0=0;address1=1;in0=0;in1=1;in2=1;in3=0;#1000 + $display("%b | %b | %b | %b | %b | %b | %b | %s | ", address0, address1, in0, in1, in2, in3, out, "1"); + address0=0;address1=1;in0=0;in1=1;in2=1;in3=1;#1000 + $display("%b | %b | %b | %b | %b | %b | %b | %s | ", address0, address1, in0, in1, in2, in3, out, "1"); + address0=0;address1=1;in0=1;in1=0;in2=0;in3=0;#1000 + $display("%b | %b | %b | %b | %b | %b | %b | %s | ", address0, address1, in0, in1, in2, in3, out, "0"); + address0=0;address1=1;in0=1;in1=0;in2=0;in3=1;#1000 + $display("%b | %b | %b | %b | %b | %b | %b | %s | ", address0, address1, in0, in1, in2, in3, out, "0"); + address0=0;address1=1;in0=1;in1=0;in2=1;in3=0;#1000 + $display("%b | %b | %b | %b | %b | %b | %b | %s | ", address0, address1, in0, in1, in2, in3, out, "1"); + address0=0;address1=1;in0=1;in1=0;in2=1;in3=1;#1000 + $display("%b | %b | %b | %b | %b | %b | %b | %s | ", address0, address1, in0, in1, in2, in3, out, "1"); + address0=0;address1=1;in0=1;in1=1;in2=0;in3=0;#1000 + $display("%b | %b | %b | %b | %b | %b | %b | %s | ", address0, address1, in0, in1, in2, in3, out, "0"); + address0=0;address1=1;in0=1;in1=1;in2=0;in3=1;#1000 + $display("%b | %b | %b | %b | %b | %b | %b | %s | ", address0, address1, in0, in1, in2, in3, out, "0"); + address0=0;address1=1;in0=1;in1=1;in2=1;in3=0;#1000 + $display("%b | %b | %b | %b | %b | %b | %b | %s | ", address0, address1, in0, in1, in2, in3, out, "1"); + address0=0;address1=1;in0=1;in1=1;in2=1;in3=1;#1000 + $display("%b | %b | %b | %b | %b | %b | %b | %s | ", address0, address1, in0, in1, in2, in3, out, "1"); + address0=1;address1=0;in0=0;in1=0;in2=0;in3=0;#1000 + $display("%b | %b | %b | %b | %b | %b | %b | %s | ", address0, address1, in0, in1, in2, in3, out, "0"); + address0=1;address1=0;in0=0;in1=0;in2=0;in3=1;#1000 + $display("%b | %b | %b | %b | %b | %b | %b | %s | ", address0, address1, in0, in1, in2, in3, out, "0"); + address0=1;address1=0;in0=0;in1=0;in2=1;in3=0;#1000 + $display("%b | %b | %b | %b | %b | %b | %b | %s | ", address0, address1, in0, in1, in2, in3, out, "0"); + address0=1;address1=0;in0=0;in1=0;in2=1;in3=1;#1000 + $display("%b | %b | %b | %b | %b | %b | %b | %s | ", address0, address1, in0, in1, in2, in3, out, "0"); + address0=1;address1=0;in0=0;in1=1;in2=0;in3=0;#1000 + $display("%b | %b | %b | %b | %b | %b | %b | %s | ", address0, address1, in0, in1, in2, in3, out, "1"); + address0=1;address1=0;in0=0;in1=1;in2=0;in3=1;#1000 + $display("%b | %b | %b | %b | %b | %b | %b | %s | ", address0, address1, in0, in1, in2, in3, out, "1"); + address0=1;address1=0;in0=0;in1=1;in2=1;in3=0;#1000 + $display("%b | %b | %b | %b | %b | %b | %b | %s | ", address0, address1, in0, in1, in2, in3, out, "1"); + address0=1;address1=0;in0=0;in1=1;in2=1;in3=1;#1000 + $display("%b | %b | %b | %b | %b | %b | %b | %s | ", address0, address1, in0, in1, in2, in3, out, "1"); + address0=1;address1=0;in0=1;in1=0;in2=0;in3=0;#1000 + $display("%b | %b | %b | %b | %b | %b | %b | %s | ", address0, address1, in0, in1, in2, in3, out, "0"); + address0=1;address1=0;in0=1;in1=0;in2=0;in3=1;#1000 + $display("%b | %b | %b | %b | %b | %b | %b | %s | ", address0, address1, in0, in1, in2, in3, out, "0"); + address0=1;address1=0;in0=1;in1=0;in2=1;in3=0;#1000 + $display("%b | %b | %b | %b | %b | %b | %b | %s | ", address0, address1, in0, in1, in2, in3, out, "0"); + address0=1;address1=0;in0=1;in1=0;in2=1;in3=1;#1000 + $display("%b | %b | %b | %b | %b | %b | %b | %s | ", address0, address1, in0, in1, in2, in3, out, "0"); + address0=1;address1=0;in0=1;in1=1;in2=0;in3=0;#1000 + $display("%b | %b | %b | %b | %b | %b | %b | %s | ", address0, address1, in0, in1, in2, in3, out, "1"); + address0=1;address1=0;in0=1;in1=1;in2=0;in3=1;#1000 + $display("%b | %b | %b | %b | %b | %b | %b | %s | ", address0, address1, in0, in1, in2, in3, out, "1"); + address0=1;address1=0;in0=1;in1=1;in2=1;in3=0;#1000 + $display("%b | %b | %b | %b | %b | %b | %b | %s | ", address0, address1, in0, in1, in2, in3, out, "1"); + address0=1;address1=0;in0=1;in1=1;in2=1;in3=1;#1000 + $display("%b | %b | %b | %b | %b | %b | %b | %s | ", address0, address1, in0, in1, in2, in3, out, "1"); + address0=1;address1=1;in0=0;in1=0;in2=0;in3=0;#1000 + $display("%b | %b | %b | %b | %b | %b | %b | %s | ", address0, address1, in0, in1, in2, in3, out, "0"); + address0=1;address1=1;in0=0;in1=0;in2=0;in3=1;#1000 + $display("%b | %b | %b | %b | %b | %b | %b | %s | ", address0, address1, in0, in1, in2, in3, out, "1"); + address0=1;address1=1;in0=0;in1=0;in2=1;in3=0;#1000 + $display("%b | %b | %b | %b | %b | %b | %b | %s | ", address0, address1, in0, in1, in2, in3, out, "0"); + address0=1;address1=1;in0=0;in1=0;in2=1;in3=1;#1000 + $display("%b | %b | %b | %b | %b | %b | %b | %s | ", address0, address1, in0, in1, in2, in3, out, "1"); + address0=1;address1=1;in0=0;in1=1;in2=0;in3=0;#1000 + $display("%b | %b | %b | %b | %b | %b | %b | %s | ", address0, address1, in0, in1, in2, in3, out, "0"); + address0=1;address1=1;in0=0;in1=1;in2=0;in3=1;#1000 + $display("%b | %b | %b | %b | %b | %b | %b | %s | ", address0, address1, in0, in1, in2, in3, out, "1"); + address0=1;address1=1;in0=0;in1=1;in2=1;in3=0;#1000 + $display("%b | %b | %b | %b | %b | %b | %b | %s | ", address0, address1, in0, in1, in2, in3, out, "0"); + address0=1;address1=1;in0=0;in1=1;in2=1;in3=1;#1000 + $display("%b | %b | %b | %b | %b | %b | %b | %s | ", address0, address1, in0, in1, in2, in3, out, "1"); + address0=1;address1=1;in0=1;in1=0;in2=0;in3=0;#1000 + $display("%b | %b | %b | %b | %b | %b | %b | %s | ", address0, address1, in0, in1, in2, in3, out, "0"); + address0=1;address1=1;in0=1;in1=0;in2=0;in3=1;#1000 + $display("%b | %b | %b | %b | %b | %b | %b | %s | ", address0, address1, in0, in1, in2, in3, out, "1"); + address0=1;address1=1;in0=1;in1=0;in2=1;in3=0;#1000 + $display("%b | %b | %b | %b | %b | %b | %b | %s | ", address0, address1, in0, in1, in2, in3, out, "0"); + address0=1;address1=1;in0=1;in1=0;in2=1;in3=1;#1000 + $display("%b | %b | %b | %b | %b | %b | %b | %s | ", address0, address1, in0, in1, in2, in3, out, "1"); + address0=1;address1=1;in0=1;in1=1;in2=0;in3=0;#1000 + $display("%b | %b | %b | %b | %b | %b | %b | %s | ", address0, address1, in0, in1, in2, in3, out, "0"); + address0=1;address1=1;in0=1;in1=1;in2=0;in3=1;#1000 + $display("%b | %b | %b | %b | %b | %b | %b | %s | ", address0, address1, in0, in1, in2, in3, out, "1"); + address0=1;address1=1;in0=1;in1=1;in2=1;in3=0;#1000 + $display("%b | %b | %b | %b | %b | %b | %b | %s | ", address0, address1, in0, in1, in2, in3, out, "0"); + address0=1;address1=1;in0=1;in1=1;in2=1;in3=1;#1000 + $display("%b | %b | %b | %b | %b | %b | %b | %s | ", address0, address1, in0, in1, in2, in3, out, "1"); + end endmodule diff --git a/multiplexer.v b/multiplexer.v index b05820f..624ddf1 100644 --- a/multiplexer.v +++ b/multiplexer.v @@ -12,6 +12,17 @@ module behavioralMultiplexer assign out = inputs[address]; endmodule +module oneBitMux( + output out, + input address, + input in0, in1 +); + wire _address, w0, w1; + `NOT nAd(_address, address); + `AND a1(w0, in0, _address); + `AND a2(w1, in1, address); + `OR o(out, w0, w1); +endmodule module structuralMultiplexer ( @@ -19,6 +30,8 @@ module structuralMultiplexer input address0, address1, input in0, in1, in2, in3 ); - // Your multiplexer code here + wire w0, w1; + oneBitMux m1(w0, address0, in0, in1); + oneBitMux m2(w1, address0, in2, in3); + oneBitMux m3(out, address1, w0, w1); endmodule - diff --git a/mux b/mux new file mode 100755 index 0000000..94e8315 --- /dev/null +++ b/mux @@ -0,0 +1,1034 @@ +#! /usr/local/bin/vvp +:ivl_version "0.10.0 (devel)" "(s20150513)"; +:ivl_delay_selection "TYPICAL"; +:vpi_time_precision - 12; +:vpi_module "system"; +:vpi_module "vhdl_sys"; +:vpi_module "v2005_math"; +:vpi_module "va_math"; +S_0x16e6f80 .scope module, "behavioralMultiplexer" "behavioralMultiplexer" 2 3; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "address0" + .port_info 2 /INPUT 1 "address1" + .port_info 3 /INPUT 1 "in0" + .port_info 4 /INPUT 1 "in1" + .port_info 5 /INPUT 1 "in2" + .port_info 6 /INPUT 1 "in3" +v0x177e690_0 .net "address", 1 0, L_0x17a0ab0; 1 drivers +o0x7fdc7c4ed048 .functor BUFZ 1, C4; HiZ drive +v0x179d700_0 .net "address0", 0 0, o0x7fdc7c4ed048; 0 drivers +o0x7fdc7c4ed078 .functor BUFZ 1, C4; HiZ drive +v0x179d7c0_0 .net "address1", 0 0, o0x7fdc7c4ed078; 0 drivers +o0x7fdc7c4ed0a8 .functor BUFZ 1, C4; HiZ drive +v0x179d890_0 .net "in0", 0 0, o0x7fdc7c4ed0a8; 0 drivers +o0x7fdc7c4ed0d8 .functor BUFZ 1, C4; HiZ drive +v0x179d950_0 .net "in1", 0 0, o0x7fdc7c4ed0d8; 0 drivers +o0x7fdc7c4ed108 .functor BUFZ 1, C4; HiZ drive +v0x179da60_0 .net "in2", 0 0, o0x7fdc7c4ed108; 0 drivers +o0x7fdc7c4ed138 .functor BUFZ 1, C4; HiZ drive +v0x179db20_0 .net "in3", 0 0, o0x7fdc7c4ed138; 0 drivers +v0x179dbe0_0 .net "inputs", 3 0, L_0x17a0a10; 1 drivers +v0x179dcc0_0 .net "out", 0 0, L_0x17a0b80; 1 drivers +L_0x17a0a10 .concat [ 1 1 1 1], o0x7fdc7c4ed0a8, o0x7fdc7c4ed0d8, o0x7fdc7c4ed108, o0x7fdc7c4ed138; +L_0x17a0ab0 .concat [ 1 1 0 0], o0x7fdc7c4ed048, o0x7fdc7c4ed078; +L_0x17a0b80 .part/v L_0x17a0a10, L_0x17a0ab0, 1; +S_0x16e6960 .scope module, "testMultiplexer" "testMultiplexer" 3 8; + .timescale -9 -12; +v0x17a0360_0 .var "address0", 0 0; +v0x17a0400_0 .var "address1", 0 0; +v0x17a0510_0 .var "in0", 0 0; +v0x17a0600_0 .var "in1", 0 0; +v0x17a06f0_0 .var "in2", 0 0; +v0x17a0830_0 .var "in3", 0 0; +v0x17a0920_0 .net "out", 0 0, L_0x17a1c40; 1 drivers +S_0x179df30 .scope module, "dut" "structuralMultiplexer" 3 13, 2 27 0, S_0x16e6960; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "address0" + .port_info 2 /INPUT 1 "address1" + .port_info 3 /INPUT 1 "in0" + .port_info 4 /INPUT 1 "in1" + .port_info 5 /INPUT 1 "in2" + .port_info 6 /INPUT 1 "in3" +v0x179fb00_0 .net "address0", 0 0, v0x17a0360_0; 1 drivers +v0x179fc10_0 .net "address1", 0 0, v0x17a0400_0; 1 drivers +v0x179fcd0_0 .net "in0", 0 0, v0x17a0510_0; 1 drivers +v0x179fda0_0 .net "in1", 0 0, v0x17a0600_0; 1 drivers +v0x179fe70_0 .net "in2", 0 0, v0x17a06f0_0; 1 drivers +v0x179ff60_0 .net "in3", 0 0, v0x17a0830_0; 1 drivers +v0x17a0030_0 .net "out", 0 0, L_0x17a1c40; alias, 1 drivers +v0x17a0100_0 .net "w0", 0 0, L_0x17a10b0; 1 drivers +v0x17a01f0_0 .net "w1", 0 0, L_0x17a1610; 1 drivers +S_0x179e180 .scope module, "m1" "oneBitMux" 2 34, 2 15 0, S_0x179df30; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "address" + .port_info 2 /INPUT 1 "in0" + .port_info 3 /INPUT 1 "in1" +L_0x17a0cf0/d .functor NOT 1, v0x17a0360_0, C4<0>, C4<0>, C4<0>; +L_0x17a0cf0 .delay 1 (50000,50000,50000) L_0x17a0cf0/d; +L_0x17a0df0/d .functor AND 1, v0x17a0510_0, L_0x17a0cf0, C4<1>, C4<1>; +L_0x17a0df0 .delay 1 (50000,50000,50000) L_0x17a0df0/d; +L_0x17a0f50/d .functor AND 1, v0x17a0600_0, v0x17a0360_0, C4<1>, C4<1>; +L_0x17a0f50 .delay 1 (50000,50000,50000) L_0x17a0f50/d; +L_0x17a10b0/d .functor OR 1, L_0x17a0df0, L_0x17a0f50, C4<0>, C4<0>; +L_0x17a10b0 .delay 1 (50000,50000,50000) L_0x17a10b0/d; +v0x179e3e0_0 .net "_address", 0 0, L_0x17a0cf0; 1 drivers +v0x179e4c0_0 .net "address", 0 0, v0x17a0360_0; alias, 1 drivers +v0x179e580_0 .net "in0", 0 0, v0x17a0510_0; alias, 1 drivers +v0x179e650_0 .net "in1", 0 0, v0x17a0600_0; alias, 1 drivers +v0x179e710_0 .net "out", 0 0, L_0x17a10b0; alias, 1 drivers +v0x179e820_0 .net "w0", 0 0, L_0x17a0df0; 1 drivers +v0x179e8e0_0 .net "w1", 0 0, L_0x17a0f50; 1 drivers +S_0x179ea20 .scope module, "m2" "oneBitMux" 2 35, 2 15 0, S_0x179df30; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "address" + .port_info 2 /INPUT 1 "in0" + .port_info 3 /INPUT 1 "in1" +L_0x17a1210/d .functor NOT 1, v0x17a0360_0, C4<0>, C4<0>, C4<0>; +L_0x17a1210 .delay 1 (50000,50000,50000) L_0x17a1210/d; +L_0x17a1370/d .functor AND 1, v0x17a06f0_0, L_0x17a1210, C4<1>, C4<1>; +L_0x17a1370 .delay 1 (50000,50000,50000) L_0x17a1370/d; +L_0x17a14b0/d .functor AND 1, v0x17a0830_0, v0x17a0360_0, C4<1>, C4<1>; +L_0x17a14b0 .delay 1 (50000,50000,50000) L_0x17a14b0/d; +L_0x17a1610/d .functor OR 1, L_0x17a1370, L_0x17a14b0, C4<0>, C4<0>; +L_0x17a1610 .delay 1 (50000,50000,50000) L_0x17a1610/d; +v0x179ec80_0 .net "_address", 0 0, L_0x17a1210; 1 drivers +v0x179ed40_0 .net "address", 0 0, v0x17a0360_0; alias, 1 drivers +v0x179ee30_0 .net "in0", 0 0, v0x17a06f0_0; alias, 1 drivers +v0x179ef00_0 .net "in1", 0 0, v0x17a0830_0; alias, 1 drivers +v0x179efa0_0 .net "out", 0 0, L_0x17a1610; alias, 1 drivers +v0x179f090_0 .net "w0", 0 0, L_0x17a1370; 1 drivers +v0x179f150_0 .net "w1", 0 0, L_0x17a14b0; 1 drivers +S_0x179f290 .scope module, "m3" "oneBitMux" 2 36, 2 15 0, S_0x179df30; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "address" + .port_info 2 /INPUT 1 "in0" + .port_info 3 /INPUT 1 "in1" +L_0x17a1770/d .functor NOT 1, v0x17a0400_0, C4<0>, C4<0>, C4<0>; +L_0x17a1770 .delay 1 (50000,50000,50000) L_0x17a1770/d; +L_0x17a18d0/d .functor AND 1, L_0x17a10b0, L_0x17a1770, C4<1>, C4<1>; +L_0x17a18d0 .delay 1 (50000,50000,50000) L_0x17a18d0/d; +L_0x17a1a50/d .functor AND 1, L_0x17a1610, v0x17a0400_0, C4<1>, C4<1>; +L_0x17a1a50 .delay 1 (50000,50000,50000) L_0x17a1a50/d; +L_0x17a1c40/d .functor OR 1, L_0x17a18d0, L_0x17a1a50, C4<0>, C4<0>; +L_0x17a1c40 .delay 1 (50000,50000,50000) L_0x17a1c40/d; +v0x179f500_0 .net "_address", 0 0, L_0x17a1770; 1 drivers +v0x179f5c0_0 .net "address", 0 0, v0x17a0400_0; alias, 1 drivers +v0x179f680_0 .net "in0", 0 0, L_0x17a10b0; alias, 1 drivers +v0x179f780_0 .net "in1", 0 0, L_0x17a1610; alias, 1 drivers +v0x179f850_0 .net "out", 0 0, L_0x17a1c40; alias, 1 drivers +v0x179f940_0 .net "w0", 0 0, L_0x17a18d0; 1 drivers +v0x179f9e0_0 .net "w1", 0 0, L_0x17a1a50; 1 drivers + .scope S_0x16e6960; +T_0 ; + %vpi_call 3 15 "$dumpfile", "mux.vcd" {0 0 0}; + %vpi_call 3 16 "$dumpvars", 32'sb00000000000000000000000000000000, S_0x16e6960 {0 0 0}; + %vpi_call 3 17 "$display", "address0 | address1 | in0 | in1 | in2 | in3 | out | out expected | " {0 0 0}; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0360_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0400_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0510_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0600_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a06f0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0830_0, 0, 1; + %delay 1000000, 0; + %vpi_call 3 19 "$display", "%b | %b | %b | %b | %b | %b | %b | %s | ", v0x17a0360_0, v0x17a0400_0, v0x17a0510_0, v0x17a0600_0, v0x17a06f0_0, v0x17a0830_0, v0x17a0920_0, "0" {0 0 0}; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0360_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0400_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0510_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0600_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a06f0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0830_0, 0, 1; + %delay 1000000, 0; + %vpi_call 3 21 "$display", "%b | %b | %b | %b | %b | %b | %b | %s | ", v0x17a0360_0, v0x17a0400_0, v0x17a0510_0, v0x17a0600_0, v0x17a06f0_0, v0x17a0830_0, v0x17a0920_0, "0" {0 0 0}; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0360_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0400_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0510_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0600_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a06f0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0830_0, 0, 1; + %delay 1000000, 0; + %vpi_call 3 23 "$display", "%b | %b | %b | %b | %b | %b | %b | %s | ", v0x17a0360_0, v0x17a0400_0, v0x17a0510_0, v0x17a0600_0, v0x17a06f0_0, v0x17a0830_0, v0x17a0920_0, "0" {0 0 0}; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0360_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0400_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0510_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0600_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a06f0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0830_0, 0, 1; + %delay 1000000, 0; + %vpi_call 3 25 "$display", "%b | %b | %b | %b | %b | %b | %b | %s | ", v0x17a0360_0, v0x17a0400_0, v0x17a0510_0, v0x17a0600_0, v0x17a06f0_0, v0x17a0830_0, v0x17a0920_0, "0" {0 0 0}; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0360_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0400_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0510_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0600_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a06f0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0830_0, 0, 1; + %delay 1000000, 0; + %vpi_call 3 27 "$display", "%b | %b | %b | %b | %b | %b | %b | %s | ", v0x17a0360_0, v0x17a0400_0, v0x17a0510_0, v0x17a0600_0, v0x17a06f0_0, v0x17a0830_0, v0x17a0920_0, "0" {0 0 0}; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0360_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0400_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0510_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0600_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a06f0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0830_0, 0, 1; + %delay 1000000, 0; + %vpi_call 3 29 "$display", "%b | %b | %b | %b | %b | %b | %b | %s | ", v0x17a0360_0, v0x17a0400_0, v0x17a0510_0, v0x17a0600_0, v0x17a06f0_0, v0x17a0830_0, v0x17a0920_0, "0" {0 0 0}; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0360_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0400_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0510_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0600_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a06f0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0830_0, 0, 1; + %delay 1000000, 0; + %vpi_call 3 31 "$display", "%b | %b | %b | %b | %b | %b | %b | %s | ", v0x17a0360_0, v0x17a0400_0, v0x17a0510_0, v0x17a0600_0, v0x17a06f0_0, v0x17a0830_0, v0x17a0920_0, "0" {0 0 0}; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0360_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0400_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0510_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0600_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a06f0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0830_0, 0, 1; + %delay 1000000, 0; + %vpi_call 3 33 "$display", "%b | %b | %b | %b | %b | %b | %b | %s | ", v0x17a0360_0, v0x17a0400_0, v0x17a0510_0, v0x17a0600_0, v0x17a06f0_0, v0x17a0830_0, v0x17a0920_0, "0" {0 0 0}; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0360_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0400_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0510_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0600_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a06f0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0830_0, 0, 1; + %delay 1000000, 0; + %vpi_call 3 35 "$display", "%b | %b | %b | %b | %b | %b | %b | %s | ", v0x17a0360_0, v0x17a0400_0, v0x17a0510_0, v0x17a0600_0, v0x17a06f0_0, v0x17a0830_0, v0x17a0920_0, "1" {0 0 0}; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0360_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0400_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0510_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0600_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a06f0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0830_0, 0, 1; + %delay 1000000, 0; + %vpi_call 3 37 "$display", "%b | %b | %b | %b | %b | %b | %b | %s | ", v0x17a0360_0, v0x17a0400_0, v0x17a0510_0, v0x17a0600_0, v0x17a06f0_0, v0x17a0830_0, v0x17a0920_0, "1" {0 0 0}; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0360_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0400_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0510_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0600_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a06f0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0830_0, 0, 1; + %delay 1000000, 0; + %vpi_call 3 39 "$display", "%b | %b | %b | %b | %b | %b | %b | %s | ", v0x17a0360_0, v0x17a0400_0, v0x17a0510_0, v0x17a0600_0, v0x17a06f0_0, v0x17a0830_0, v0x17a0920_0, "1" {0 0 0}; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0360_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0400_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0510_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0600_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a06f0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0830_0, 0, 1; + %delay 1000000, 0; + %vpi_call 3 41 "$display", "%b | %b | %b | %b | %b | %b | %b | %s | ", v0x17a0360_0, v0x17a0400_0, v0x17a0510_0, v0x17a0600_0, v0x17a06f0_0, v0x17a0830_0, v0x17a0920_0, "1" {0 0 0}; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0360_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0400_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0510_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0600_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a06f0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0830_0, 0, 1; + %delay 1000000, 0; + %vpi_call 3 43 "$display", "%b | %b | %b | %b | %b | %b | %b | %s | ", v0x17a0360_0, v0x17a0400_0, v0x17a0510_0, v0x17a0600_0, v0x17a06f0_0, v0x17a0830_0, v0x17a0920_0, "1" {0 0 0}; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0360_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0400_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0510_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0600_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a06f0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0830_0, 0, 1; + %delay 1000000, 0; + %vpi_call 3 45 "$display", "%b | %b | %b | %b | %b | %b | %b | %s | ", v0x17a0360_0, v0x17a0400_0, v0x17a0510_0, v0x17a0600_0, v0x17a06f0_0, v0x17a0830_0, v0x17a0920_0, "1" {0 0 0}; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0360_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0400_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0510_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0600_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a06f0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0830_0, 0, 1; + %delay 1000000, 0; + %vpi_call 3 47 "$display", "%b | %b | %b | %b | %b | %b | %b | %s | ", v0x17a0360_0, v0x17a0400_0, v0x17a0510_0, v0x17a0600_0, v0x17a06f0_0, v0x17a0830_0, v0x17a0920_0, "1" {0 0 0}; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0360_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0400_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0510_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0600_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a06f0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0830_0, 0, 1; + %delay 1000000, 0; + %vpi_call 3 49 "$display", "%b | %b | %b | %b | %b | %b | %b | %s | ", v0x17a0360_0, v0x17a0400_0, v0x17a0510_0, v0x17a0600_0, v0x17a06f0_0, v0x17a0830_0, v0x17a0920_0, "1" {0 0 0}; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0360_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0400_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0510_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0600_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a06f0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0830_0, 0, 1; + %delay 1000000, 0; + %vpi_call 3 51 "$display", "%b | %b | %b | %b | %b | %b | %b | %s | ", v0x17a0360_0, v0x17a0400_0, v0x17a0510_0, v0x17a0600_0, v0x17a06f0_0, v0x17a0830_0, v0x17a0920_0, "0" {0 0 0}; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0360_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0400_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0510_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0600_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a06f0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0830_0, 0, 1; + %delay 1000000, 0; + %vpi_call 3 53 "$display", "%b | %b | %b | %b | %b | %b | %b | %s | ", v0x17a0360_0, v0x17a0400_0, v0x17a0510_0, v0x17a0600_0, v0x17a06f0_0, v0x17a0830_0, v0x17a0920_0, "0" {0 0 0}; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0360_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0400_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0510_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0600_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a06f0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0830_0, 0, 1; + %delay 1000000, 0; + %vpi_call 3 55 "$display", "%b | %b | %b | %b | %b | %b | %b | %s | ", v0x17a0360_0, v0x17a0400_0, v0x17a0510_0, v0x17a0600_0, v0x17a06f0_0, v0x17a0830_0, v0x17a0920_0, "1" {0 0 0}; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0360_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0400_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0510_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0600_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a06f0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0830_0, 0, 1; + %delay 1000000, 0; + %vpi_call 3 57 "$display", "%b | %b | %b | %b | %b | %b | %b | %s | ", v0x17a0360_0, v0x17a0400_0, v0x17a0510_0, v0x17a0600_0, v0x17a06f0_0, v0x17a0830_0, v0x17a0920_0, "1" {0 0 0}; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0360_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0400_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0510_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0600_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a06f0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0830_0, 0, 1; + %delay 1000000, 0; + %vpi_call 3 59 "$display", "%b | %b | %b | %b | %b | %b | %b | %s | ", v0x17a0360_0, v0x17a0400_0, v0x17a0510_0, v0x17a0600_0, v0x17a06f0_0, v0x17a0830_0, v0x17a0920_0, "0" {0 0 0}; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0360_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0400_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0510_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0600_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a06f0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0830_0, 0, 1; + %delay 1000000, 0; + %vpi_call 3 61 "$display", "%b | %b | %b | %b | %b | %b | %b | %s | ", v0x17a0360_0, v0x17a0400_0, v0x17a0510_0, v0x17a0600_0, v0x17a06f0_0, v0x17a0830_0, v0x17a0920_0, "0" {0 0 0}; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0360_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0400_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0510_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0600_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a06f0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0830_0, 0, 1; + %delay 1000000, 0; + %vpi_call 3 63 "$display", "%b | %b | %b | %b | %b | %b | %b | %s | ", v0x17a0360_0, v0x17a0400_0, v0x17a0510_0, v0x17a0600_0, v0x17a06f0_0, v0x17a0830_0, v0x17a0920_0, "1" {0 0 0}; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0360_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0400_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0510_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0600_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a06f0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0830_0, 0, 1; + %delay 1000000, 0; + %vpi_call 3 65 "$display", "%b | %b | %b | %b | %b | %b | %b | %s | ", v0x17a0360_0, v0x17a0400_0, v0x17a0510_0, v0x17a0600_0, v0x17a06f0_0, v0x17a0830_0, v0x17a0920_0, "1" {0 0 0}; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0360_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0400_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0510_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0600_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a06f0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0830_0, 0, 1; + %delay 1000000, 0; + %vpi_call 3 67 "$display", "%b | %b | %b | %b | %b | %b | %b | %s | ", v0x17a0360_0, v0x17a0400_0, v0x17a0510_0, v0x17a0600_0, v0x17a06f0_0, v0x17a0830_0, v0x17a0920_0, "0" {0 0 0}; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0360_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0400_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0510_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0600_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a06f0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0830_0, 0, 1; + %delay 1000000, 0; + %vpi_call 3 69 "$display", "%b | %b | %b | %b | %b | %b | %b | %s | ", v0x17a0360_0, v0x17a0400_0, v0x17a0510_0, v0x17a0600_0, v0x17a06f0_0, v0x17a0830_0, v0x17a0920_0, "0" {0 0 0}; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0360_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0400_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0510_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0600_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a06f0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0830_0, 0, 1; + %delay 1000000, 0; + %vpi_call 3 71 "$display", "%b | %b | %b | %b | %b | %b | %b | %s | ", v0x17a0360_0, v0x17a0400_0, v0x17a0510_0, v0x17a0600_0, v0x17a06f0_0, v0x17a0830_0, v0x17a0920_0, "1" {0 0 0}; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0360_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0400_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0510_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0600_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a06f0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0830_0, 0, 1; + %delay 1000000, 0; + %vpi_call 3 73 "$display", "%b | %b | %b | %b | %b | %b | %b | %s | ", v0x17a0360_0, v0x17a0400_0, v0x17a0510_0, v0x17a0600_0, v0x17a06f0_0, v0x17a0830_0, v0x17a0920_0, "1" {0 0 0}; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0360_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0400_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0510_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0600_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a06f0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0830_0, 0, 1; + %delay 1000000, 0; + %vpi_call 3 75 "$display", "%b | %b | %b | %b | %b | %b | %b | %s | ", v0x17a0360_0, v0x17a0400_0, v0x17a0510_0, v0x17a0600_0, v0x17a06f0_0, v0x17a0830_0, v0x17a0920_0, "0" {0 0 0}; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0360_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0400_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0510_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0600_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a06f0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0830_0, 0, 1; + %delay 1000000, 0; + %vpi_call 3 77 "$display", "%b | %b | %b | %b | %b | %b | %b | %s | ", v0x17a0360_0, v0x17a0400_0, v0x17a0510_0, v0x17a0600_0, v0x17a06f0_0, v0x17a0830_0, v0x17a0920_0, "0" {0 0 0}; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0360_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0400_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0510_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0600_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a06f0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0830_0, 0, 1; + %delay 1000000, 0; + %vpi_call 3 79 "$display", "%b | %b | %b | %b | %b | %b | %b | %s | ", v0x17a0360_0, v0x17a0400_0, v0x17a0510_0, v0x17a0600_0, v0x17a06f0_0, v0x17a0830_0, v0x17a0920_0, "1" {0 0 0}; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0360_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0400_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0510_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0600_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a06f0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0830_0, 0, 1; + %delay 1000000, 0; + %vpi_call 3 81 "$display", "%b | %b | %b | %b | %b | %b | %b | %s | ", v0x17a0360_0, v0x17a0400_0, v0x17a0510_0, v0x17a0600_0, v0x17a06f0_0, v0x17a0830_0, v0x17a0920_0, "1" {0 0 0}; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0360_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0400_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0510_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0600_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a06f0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0830_0, 0, 1; + %delay 1000000, 0; + %vpi_call 3 83 "$display", "%b | %b | %b | %b | %b | %b | %b | %s | ", v0x17a0360_0, v0x17a0400_0, v0x17a0510_0, v0x17a0600_0, v0x17a06f0_0, v0x17a0830_0, v0x17a0920_0, "0" {0 0 0}; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0360_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0400_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0510_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0600_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a06f0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0830_0, 0, 1; + %delay 1000000, 0; + %vpi_call 3 85 "$display", "%b | %b | %b | %b | %b | %b | %b | %s | ", v0x17a0360_0, v0x17a0400_0, v0x17a0510_0, v0x17a0600_0, v0x17a06f0_0, v0x17a0830_0, v0x17a0920_0, "0" {0 0 0}; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0360_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0400_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0510_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0600_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a06f0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0830_0, 0, 1; + %delay 1000000, 0; + %vpi_call 3 87 "$display", "%b | %b | %b | %b | %b | %b | %b | %s | ", v0x17a0360_0, v0x17a0400_0, v0x17a0510_0, v0x17a0600_0, v0x17a06f0_0, v0x17a0830_0, v0x17a0920_0, "0" {0 0 0}; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0360_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0400_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0510_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0600_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a06f0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0830_0, 0, 1; + %delay 1000000, 0; + %vpi_call 3 89 "$display", "%b | %b | %b | %b | %b | %b | %b | %s | ", v0x17a0360_0, v0x17a0400_0, v0x17a0510_0, v0x17a0600_0, v0x17a06f0_0, v0x17a0830_0, v0x17a0920_0, "0" {0 0 0}; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0360_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0400_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0510_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0600_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a06f0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0830_0, 0, 1; + %delay 1000000, 0; + %vpi_call 3 91 "$display", "%b | %b | %b | %b | %b | %b | %b | %s | ", v0x17a0360_0, v0x17a0400_0, v0x17a0510_0, v0x17a0600_0, v0x17a06f0_0, v0x17a0830_0, v0x17a0920_0, "1" {0 0 0}; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0360_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0400_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0510_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0600_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a06f0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0830_0, 0, 1; + %delay 1000000, 0; + %vpi_call 3 93 "$display", "%b | %b | %b | %b | %b | %b | %b | %s | ", v0x17a0360_0, v0x17a0400_0, v0x17a0510_0, v0x17a0600_0, v0x17a06f0_0, v0x17a0830_0, v0x17a0920_0, "1" {0 0 0}; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0360_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0400_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0510_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0600_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a06f0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0830_0, 0, 1; + %delay 1000000, 0; + %vpi_call 3 95 "$display", "%b | %b | %b | %b | %b | %b | %b | %s | ", v0x17a0360_0, v0x17a0400_0, v0x17a0510_0, v0x17a0600_0, v0x17a06f0_0, v0x17a0830_0, v0x17a0920_0, "1" {0 0 0}; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0360_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0400_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0510_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0600_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a06f0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0830_0, 0, 1; + %delay 1000000, 0; + %vpi_call 3 97 "$display", "%b | %b | %b | %b | %b | %b | %b | %s | ", v0x17a0360_0, v0x17a0400_0, v0x17a0510_0, v0x17a0600_0, v0x17a06f0_0, v0x17a0830_0, v0x17a0920_0, "1" {0 0 0}; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0360_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0400_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0510_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0600_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a06f0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0830_0, 0, 1; + %delay 1000000, 0; + %vpi_call 3 99 "$display", "%b | %b | %b | %b | %b | %b | %b | %s | ", v0x17a0360_0, v0x17a0400_0, v0x17a0510_0, v0x17a0600_0, v0x17a06f0_0, v0x17a0830_0, v0x17a0920_0, "0" {0 0 0}; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0360_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0400_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0510_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0600_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a06f0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0830_0, 0, 1; + %delay 1000000, 0; + %vpi_call 3 101 "$display", "%b | %b | %b | %b | %b | %b | %b | %s | ", v0x17a0360_0, v0x17a0400_0, v0x17a0510_0, v0x17a0600_0, v0x17a06f0_0, v0x17a0830_0, v0x17a0920_0, "0" {0 0 0}; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0360_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0400_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0510_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0600_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a06f0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0830_0, 0, 1; + %delay 1000000, 0; + %vpi_call 3 103 "$display", "%b | %b | %b | %b | %b | %b | %b | %s | ", v0x17a0360_0, v0x17a0400_0, v0x17a0510_0, v0x17a0600_0, v0x17a06f0_0, v0x17a0830_0, v0x17a0920_0, "0" {0 0 0}; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0360_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0400_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0510_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0600_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a06f0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0830_0, 0, 1; + %delay 1000000, 0; + %vpi_call 3 105 "$display", "%b | %b | %b | %b | %b | %b | %b | %s | ", v0x17a0360_0, v0x17a0400_0, v0x17a0510_0, v0x17a0600_0, v0x17a06f0_0, v0x17a0830_0, v0x17a0920_0, "0" {0 0 0}; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0360_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0400_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0510_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0600_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a06f0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0830_0, 0, 1; + %delay 1000000, 0; + %vpi_call 3 107 "$display", "%b | %b | %b | %b | %b | %b | %b | %s | ", v0x17a0360_0, v0x17a0400_0, v0x17a0510_0, v0x17a0600_0, v0x17a06f0_0, v0x17a0830_0, v0x17a0920_0, "1" {0 0 0}; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0360_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0400_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0510_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0600_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a06f0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0830_0, 0, 1; + %delay 1000000, 0; + %vpi_call 3 109 "$display", "%b | %b | %b | %b | %b | %b | %b | %s | ", v0x17a0360_0, v0x17a0400_0, v0x17a0510_0, v0x17a0600_0, v0x17a06f0_0, v0x17a0830_0, v0x17a0920_0, "1" {0 0 0}; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0360_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0400_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0510_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0600_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a06f0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0830_0, 0, 1; + %delay 1000000, 0; + %vpi_call 3 111 "$display", "%b | %b | %b | %b | %b | %b | %b | %s | ", v0x17a0360_0, v0x17a0400_0, v0x17a0510_0, v0x17a0600_0, v0x17a06f0_0, v0x17a0830_0, v0x17a0920_0, "1" {0 0 0}; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0360_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0400_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0510_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0600_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a06f0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0830_0, 0, 1; + %delay 1000000, 0; + %vpi_call 3 113 "$display", "%b | %b | %b | %b | %b | %b | %b | %s | ", v0x17a0360_0, v0x17a0400_0, v0x17a0510_0, v0x17a0600_0, v0x17a06f0_0, v0x17a0830_0, v0x17a0920_0, "1" {0 0 0}; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0360_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0400_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0510_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0600_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a06f0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0830_0, 0, 1; + %delay 1000000, 0; + %vpi_call 3 115 "$display", "%b | %b | %b | %b | %b | %b | %b | %s | ", v0x17a0360_0, v0x17a0400_0, v0x17a0510_0, v0x17a0600_0, v0x17a06f0_0, v0x17a0830_0, v0x17a0920_0, "0" {0 0 0}; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0360_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0400_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0510_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0600_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a06f0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0830_0, 0, 1; + %delay 1000000, 0; + %vpi_call 3 117 "$display", "%b | %b | %b | %b | %b | %b | %b | %s | ", v0x17a0360_0, v0x17a0400_0, v0x17a0510_0, v0x17a0600_0, v0x17a06f0_0, v0x17a0830_0, v0x17a0920_0, "1" {0 0 0}; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0360_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0400_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0510_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0600_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a06f0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0830_0, 0, 1; + %delay 1000000, 0; + %vpi_call 3 119 "$display", "%b | %b | %b | %b | %b | %b | %b | %s | ", v0x17a0360_0, v0x17a0400_0, v0x17a0510_0, v0x17a0600_0, v0x17a06f0_0, v0x17a0830_0, v0x17a0920_0, "0" {0 0 0}; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0360_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0400_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0510_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0600_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a06f0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0830_0, 0, 1; + %delay 1000000, 0; + %vpi_call 3 121 "$display", "%b | %b | %b | %b | %b | %b | %b | %s | ", v0x17a0360_0, v0x17a0400_0, v0x17a0510_0, v0x17a0600_0, v0x17a06f0_0, v0x17a0830_0, v0x17a0920_0, "1" {0 0 0}; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0360_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0400_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0510_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0600_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a06f0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0830_0, 0, 1; + %delay 1000000, 0; + %vpi_call 3 123 "$display", "%b | %b | %b | %b | %b | %b | %b | %s | ", v0x17a0360_0, v0x17a0400_0, v0x17a0510_0, v0x17a0600_0, v0x17a06f0_0, v0x17a0830_0, v0x17a0920_0, "0" {0 0 0}; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0360_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0400_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0510_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0600_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a06f0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0830_0, 0, 1; + %delay 1000000, 0; + %vpi_call 3 125 "$display", "%b | %b | %b | %b | %b | %b | %b | %s | ", v0x17a0360_0, v0x17a0400_0, v0x17a0510_0, v0x17a0600_0, v0x17a06f0_0, v0x17a0830_0, v0x17a0920_0, "1" {0 0 0}; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0360_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0400_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0510_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0600_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a06f0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0830_0, 0, 1; + %delay 1000000, 0; + %vpi_call 3 127 "$display", "%b | %b | %b | %b | %b | %b | %b | %s | ", v0x17a0360_0, v0x17a0400_0, v0x17a0510_0, v0x17a0600_0, v0x17a06f0_0, v0x17a0830_0, v0x17a0920_0, "0" {0 0 0}; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0360_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0400_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0510_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0600_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a06f0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0830_0, 0, 1; + %delay 1000000, 0; + %vpi_call 3 129 "$display", "%b | %b | %b | %b | %b | %b | %b | %s | ", v0x17a0360_0, v0x17a0400_0, v0x17a0510_0, v0x17a0600_0, v0x17a06f0_0, v0x17a0830_0, v0x17a0920_0, "1" {0 0 0}; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0360_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0400_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0510_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0600_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a06f0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0830_0, 0, 1; + %delay 1000000, 0; + %vpi_call 3 131 "$display", "%b | %b | %b | %b | %b | %b | %b | %s | ", v0x17a0360_0, v0x17a0400_0, v0x17a0510_0, v0x17a0600_0, v0x17a06f0_0, v0x17a0830_0, v0x17a0920_0, "0" {0 0 0}; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0360_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0400_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0510_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0600_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a06f0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0830_0, 0, 1; + %delay 1000000, 0; + %vpi_call 3 133 "$display", "%b | %b | %b | %b | %b | %b | %b | %s | ", v0x17a0360_0, v0x17a0400_0, v0x17a0510_0, v0x17a0600_0, v0x17a06f0_0, v0x17a0830_0, v0x17a0920_0, "1" {0 0 0}; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0360_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0400_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0510_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0600_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a06f0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0830_0, 0, 1; + %delay 1000000, 0; + %vpi_call 3 135 "$display", "%b | %b | %b | %b | %b | %b | %b | %s | ", v0x17a0360_0, v0x17a0400_0, v0x17a0510_0, v0x17a0600_0, v0x17a06f0_0, v0x17a0830_0, v0x17a0920_0, "0" {0 0 0}; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0360_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0400_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0510_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0600_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a06f0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0830_0, 0, 1; + %delay 1000000, 0; + %vpi_call 3 137 "$display", "%b | %b | %b | %b | %b | %b | %b | %s | ", v0x17a0360_0, v0x17a0400_0, v0x17a0510_0, v0x17a0600_0, v0x17a06f0_0, v0x17a0830_0, v0x17a0920_0, "1" {0 0 0}; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0360_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0400_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0510_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0600_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a06f0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0830_0, 0, 1; + %delay 1000000, 0; + %vpi_call 3 139 "$display", "%b | %b | %b | %b | %b | %b | %b | %s | ", v0x17a0360_0, v0x17a0400_0, v0x17a0510_0, v0x17a0600_0, v0x17a06f0_0, v0x17a0830_0, v0x17a0920_0, "0" {0 0 0}; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0360_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0400_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0510_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0600_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a06f0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0830_0, 0, 1; + %delay 1000000, 0; + %vpi_call 3 141 "$display", "%b | %b | %b | %b | %b | %b | %b | %s | ", v0x17a0360_0, v0x17a0400_0, v0x17a0510_0, v0x17a0600_0, v0x17a06f0_0, v0x17a0830_0, v0x17a0920_0, "1" {0 0 0}; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0360_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0400_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0510_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0600_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a06f0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x17a0830_0, 0, 1; + %delay 1000000, 0; + %vpi_call 3 143 "$display", "%b | %b | %b | %b | %b | %b | %b | %s | ", v0x17a0360_0, v0x17a0400_0, v0x17a0510_0, v0x17a0600_0, v0x17a06f0_0, v0x17a0830_0, v0x17a0920_0, "0" {0 0 0}; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0360_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0400_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0510_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0600_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a06f0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x17a0830_0, 0, 1; + %delay 1000000, 0; + %vpi_call 3 145 "$display", "%b | %b | %b | %b | %b | %b | %b | %s | ", v0x17a0360_0, v0x17a0400_0, v0x17a0510_0, v0x17a0600_0, v0x17a06f0_0, v0x17a0830_0, v0x17a0920_0, "1" {0 0 0}; + %end; + .thread T_0; +# The file index is used to find the file name in the following table. +:file_names 4; + "N/A"; + ""; + "./multiplexer.v"; + "multiplexer.t.v"; diff --git a/mux.vcd b/mux.vcd new file mode 100644 index 0000000..d168774 --- /dev/null +++ b/mux.vcd @@ -0,0 +1,617 @@ +$date + Thu Sep 21 21:30:20 2017 +$end +$version + Icarus Verilog +$end +$timescale + 1ps +$end +$scope module testMultiplexer $end +$var wire 1 ! out $end +$var reg 1 " address0 $end +$var reg 1 # address1 $end +$var reg 1 $ in0 $end +$var reg 1 % in1 $end +$var reg 1 & in2 $end +$var reg 1 ' in3 $end +$scope module dut $end +$var wire 1 " address0 $end +$var wire 1 # address1 $end +$var wire 1 $ in0 $end +$var wire 1 % in1 $end +$var wire 1 & in2 $end +$var wire 1 ' in3 $end +$var wire 1 ( w1 $end +$var wire 1 ) w0 $end +$var wire 1 ! out $end +$scope module m1 $end +$var wire 1 * _address $end +$var wire 1 " address $end +$var wire 1 $ in0 $end +$var wire 1 % in1 $end +$var wire 1 ) out $end +$var wire 1 + w0 $end +$var wire 1 , w1 $end +$upscope $end +$scope module m2 $end +$var wire 1 - _address $end +$var wire 1 " address $end +$var wire 1 & in0 $end +$var wire 1 ' in1 $end +$var wire 1 ( out $end +$var wire 1 . w0 $end +$var wire 1 / w1 $end +$upscope $end +$scope module m3 $end +$var wire 1 0 _address $end +$var wire 1 # address $end +$var wire 1 ) in0 $end +$var wire 1 ( in1 $end +$var wire 1 ! out $end +$var wire 1 1 w0 $end +$var wire 1 2 w1 $end +$upscope $end +$upscope $end +$upscope $end +$enddefinitions $end +#0 +$dumpvars +x2 +x1 +x0 +x/ +x. +x- +x, +x+ +x* +x) +x( +0' +0& +0% +0$ +0# +0" +x! +$end +#50000 +10 +1* +1- +02 +0/ +0. +0, +0+ +#100000 +0( +0) +#150000 +01 +#200000 +0! +#1000000 +1' +#2000000 +0' +1& +#2050000 +1. +#2100000 +1( +#3000000 +1' +#4000000 +0' +0& +1% +#4050000 +0. +#4100000 +0( +#5000000 +1' +#6000000 +0' +1& +#6050000 +1. +#6100000 +1( +#7000000 +1' +#8000000 +0' +0& +0% +1$ +#8050000 +0. +1+ +#8100000 +0( +1) +#8150000 +11 +#8200000 +1! +#9000000 +1' +#10000000 +0' +1& +#10050000 +1. +#10100000 +1( +#11000000 +1' +#12000000 +0' +0& +1% +#12050000 +0. +#12100000 +0( +#13000000 +1' +#14000000 +0' +1& +#14050000 +1. +#14100000 +1( +#15000000 +1' +#16000000 +0' +0& +0% +0$ +1# +#16050000 +0. +0+ +00 +12 +#16100000 +0( +0) +01 +#16150000 +02 +#16200000 +0! +#17000000 +1' +#18000000 +0' +1& +#18050000 +1. +#18100000 +1( +#18150000 +12 +#18200000 +1! +#19000000 +1' +#20000000 +0' +0& +1% +#20050000 +0. +#20100000 +0( +#20150000 +02 +#20200000 +0! +#21000000 +1' +#22000000 +0' +1& +#22050000 +1. +#22100000 +1( +#22150000 +12 +#22200000 +1! +#23000000 +1' +#24000000 +0' +0& +0% +1$ +#24050000 +0. +1+ +#24100000 +0( +1) +#24150000 +02 +#24200000 +0! +#25000000 +1' +#26000000 +0' +1& +#26050000 +1. +#26100000 +1( +#26150000 +12 +#26200000 +1! +#27000000 +1' +#28000000 +0' +0& +1% +#28050000 +0. +#28100000 +0( +#28150000 +02 +#28200000 +0! +#29000000 +1' +#30000000 +0' +1& +#30050000 +1. +#30100000 +1( +#30150000 +12 +#30200000 +1! +#31000000 +1' +#32000000 +0' +0& +0% +0$ +0# +1" +#32050000 +0. +0+ +10 +02 +0* +0- +#32100000 +0( +0) +11 +0! +#32150000 +01 +1! +#32200000 +0! +#33000000 +1' +#33050000 +1/ +#33100000 +1( +#34000000 +0' +1& +#34050000 +0/ +#34100000 +0( +#35000000 +1' +#35050000 +1/ +#35100000 +1( +#36000000 +0' +0& +1% +#36050000 +0/ +1, +#36100000 +0( +1) +#36150000 +11 +#36200000 +1! +#37000000 +1' +#37050000 +1/ +#37100000 +1( +#38000000 +0' +1& +#38050000 +0/ +#38100000 +0( +#39000000 +1' +#39050000 +1/ +#39100000 +1( +#40000000 +0' +0& +0% +1$ +#40050000 +0/ +0, +#40100000 +0( +0) +#40150000 +01 +#40200000 +0! +#41000000 +1' +#41050000 +1/ +#41100000 +1( +#42000000 +0' +1& +#42050000 +0/ +#42100000 +0( +#43000000 +1' +#43050000 +1/ +#43100000 +1( +#44000000 +0' +0& +1% +#44050000 +0/ +1, +#44100000 +0( +1) +#44150000 +11 +#44200000 +1! +#45000000 +1' +#45050000 +1/ +#45100000 +1( +#46000000 +0' +1& +#46050000 +0/ +#46100000 +0( +#47000000 +1' +#47050000 +1/ +#47100000 +1( +#48000000 +0' +0& +0% +0$ +1# +#48050000 +0/ +0, +00 +12 +#48100000 +0( +0) +01 +#48150000 +02 +#48200000 +0! +#49000000 +1' +#49050000 +1/ +#49100000 +1( +#49150000 +12 +#49200000 +1! +#50000000 +0' +1& +#50050000 +0/ +#50100000 +0( +#50150000 +02 +#50200000 +0! +#51000000 +1' +#51050000 +1/ +#51100000 +1( +#51150000 +12 +#51200000 +1! +#52000000 +0' +0& +1% +#52050000 +0/ +1, +#52100000 +0( +1) +#52150000 +02 +#52200000 +0! +#53000000 +1' +#53050000 +1/ +#53100000 +1( +#53150000 +12 +#53200000 +1! +#54000000 +0' +1& +#54050000 +0/ +#54100000 +0( +#54150000 +02 +#54200000 +0! +#55000000 +1' +#55050000 +1/ +#55100000 +1( +#55150000 +12 +#55200000 +1! +#56000000 +0' +0& +0% +1$ +#56050000 +0/ +0, +#56100000 +0( +0) +#56150000 +02 +#56200000 +0! +#57000000 +1' +#57050000 +1/ +#57100000 +1( +#57150000 +12 +#57200000 +1! +#58000000 +0' +1& +#58050000 +0/ +#58100000 +0( +#58150000 +02 +#58200000 +0! +#59000000 +1' +#59050000 +1/ +#59100000 +1( +#59150000 +12 +#59200000 +1! +#60000000 +0' +0& +1% +#60050000 +0/ +1, +#60100000 +0( +1) +#60150000 +02 +#60200000 +0! +#61000000 +1' +#61050000 +1/ +#61100000 +1( +#61150000 +12 +#61200000 +1! +#62000000 +0' +1& +#62050000 +0/ +#62100000 +0( +#62150000 +02 +#62200000 +0! +#63000000 +1' +#63050000 +1/ +#63100000 +1( +#63150000 +12 +#63200000 +1! +#64000000 diff --git a/muxTable.txt b/muxTable.txt new file mode 100644 index 0000000..6ba80ef --- /dev/null +++ b/muxTable.txt @@ -0,0 +1,65 @@ +address0 | address1 | in0 | in1 | in2 | in3 | out | out expected | +0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | +0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | +0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | +0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | +0 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | +0 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | +0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | +0 | 0 | 1 | 0 | 1 | 0 | 1 | 1 | +0 | 0 | 1 | 0 | 1 | 1 | 1 | 1 | +0 | 0 | 1 | 1 | 0 | 0 | 1 | 1 | +0 | 0 | 1 | 1 | 0 | 1 | 1 | 1 | +0 | 0 | 1 | 1 | 1 | 0 | 1 | 1 | +0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | +0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | +0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | +0 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | +0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | +0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | +0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | +0 | 1 | 0 | 1 | 1 | 0 | 1 | 1 | +0 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | +0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | +0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | +0 | 1 | 1 | 0 | 1 | 0 | 1 | 1 | +0 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | +0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | +0 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | +0 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | +0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | +1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +1 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | +1 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | +1 | 0 | 0 | 1 | 0 | 1 | 1 | 1 | +1 | 0 | 0 | 1 | 1 | 0 | 1 | 1 | +1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | +1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | +1 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | +1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | +1 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | +1 | 0 | 1 | 1 | 0 | 0 | 1 | 1 | +1 | 0 | 1 | 1 | 0 | 1 | 1 | 1 | +1 | 0 | 1 | 1 | 1 | 0 | 1 | 1 | +1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | +1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | +1 | 1 | 0 | 0 | 0 | 1 | 1 | 1 | +1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | +1 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | +1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | +1 | 1 | 0 | 1 | 0 | 1 | 1 | 1 | +1 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | +1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | +1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | +1 | 1 | 1 | 0 | 0 | 1 | 1 | 1 | +1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | +1 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | +1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | +1 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | +1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | +1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | diff --git a/muxTrace.png b/muxTrace.png new file mode 100644 index 0000000..afbb725 Binary files /dev/null and b/muxTrace.png differ diff --git a/writeup.pdf b/writeup.pdf new file mode 100644 index 0000000..f1cfa74 Binary files /dev/null and b/writeup.pdf differ