diff --git a/adder.t.v b/adder.t.v index 76109ed..c0e314f 100644 --- a/adder.t.v +++ b/adder.t.v @@ -3,12 +3,31 @@ `include "adder.v" module testFullAdder(); + reg a, b, carryin; wire sum, carryout; - behavioralFullAdder adder (sum, carryout, a, b, carryin); + structuralFullAdder adder (sum, carryout, a, b, carryin); initial begin - // Your test code here + $dumpfile("adder_trace.vcd"); + $dumpvars; + $display(" A B Cin | S Cout | Expected Output"); + a=0;b=0;carryin=0; #1000 + $display(" %b %b %b | %b %b | All False", a, b, carryin, sum, carryout); + a=0;b=0;carryin=1; #1000 + $display(" %b %b %b | %b %b | S Only", a, b, carryin, sum, carryout); + a=0;b=1;carryin=0; #1000 + $display(" %b %b %b | %b %b | S Only", a, b, carryin, sum, carryout); + a=0;b=1;carryin=1; #1000 + $display(" %b %b %b | %b %b | Cout Only", a, b, carryin, sum, carryout); + a=1;b=0;carryin=0; #1000 + $display(" %b %b %b | %b %b | S Only", a, b, carryin, sum, carryout); + a=1;b=0;carryin=1; #1000 + $display(" %b %b %b | %b %b | Cout Only", a, b, carryin, sum, carryout); + a=1;b=1;carryin=0; #1000 + $display(" %b %b %b | %b %b | Cout Only", a, b, carryin, sum, carryout); + a=1;b=1;carryin=1; #1000 + $display(" %b %b %b | %b %b | All True", a, b, carryin, sum, carryout); end endmodule diff --git a/adder.v b/adder.v index d21f7e4..6911a07 100644 --- a/adder.v +++ b/adder.v @@ -1,5 +1,11 @@ // Adder circuit +// define gates with delays +`define AND and #50 +`define OR or #50 +`define XOR xor #50 +`define NOT not #50 + module behavioralFullAdder ( output sum, @@ -20,5 +26,14 @@ module structuralFullAdder input b, input carryin ); - // Your adder code here + + wire ab; + `XOR aXORb(ab, a, b); + `XOR abXORc(sum, ab, carryin); + + wire aAndb, oneAndC; + `AND aANDb(aAndb, a, b); + `AND aXORbANDc(oneAndC, ab, carryin); + `OR aorborc(carryout, aAndb, oneAndC); + endmodule diff --git a/adder_table.png b/adder_table.png new file mode 100644 index 0000000..a389138 Binary files /dev/null and b/adder_table.png differ diff --git a/adder_wave.png b/adder_wave.png new file mode 100644 index 0000000..8e6bfc5 Binary files /dev/null and b/adder_wave.png differ diff --git a/decoder.t.v b/decoder.t.v index e0e925f..e2bdf8e 100644 --- a/decoder.t.v +++ b/decoder.t.v @@ -7,10 +7,15 @@ module testDecoder (); reg enable; wire out0,out1,out2,out3; - behavioralDecoder decoder (out0,out1,out2,out3,addr0,addr1,enable); + + structuralDecoder decoder (out0,out1,out2,out3,addr0,addr1,enable); //structuralDecoder decoder (out0,out1,out2,out3,addr0,addr1,enable); // Swap after testing initial begin + + $dumpfile("decoder_trace.vcd"); + $dumpvars; + $display("En A0 A1| O0 O1 O2 O3 | Expected Output"); enable=0;addr0=0;addr1=0; #1000 $display("%b %b %b | %b %b %b %b | All false", enable, addr0, addr1, out0, out1, out2, out3); diff --git a/decoder.v b/decoder.v index 17836e0..897d7c4 100644 --- a/decoder.v +++ b/decoder.v @@ -1,5 +1,10 @@ // Decoder circuit +// define gates with delays +`define AND and #100 +`define OR or #100 +`define NOT not #100 + module behavioralDecoder ( output out0, out1, out2, out3, @@ -17,6 +22,17 @@ module structuralDecoder input address0, address1, input enable ); - // Your decoder code here + wire _0, _1; + `NOT inv0(_0, address0); + `NOT inv1(_1, address1); + wire choose0, choose1, choose2, choose3; + `AND _0AND_1(choose0, _0, _1); + `AND a0AND_1(choose1, address0, _1); + `AND _0ANDa1(choose2, _0, address1); + `AND a0ANDa1(choose3, address0, address1); + `AND ifEnable0(out0, enable, choose0); + `AND ifEnable1(out1, enable, choose1); + `AND ifEnable2(out2, enable, choose2); + `AND ifEnable3(out3, enable, choose3); endmodule diff --git a/decoder_table.png b/decoder_table.png new file mode 100644 index 0000000..88c6cd9 Binary files /dev/null and b/decoder_table.png differ diff --git a/decoder_wave.png b/decoder_wave.png new file mode 100644 index 0000000..7c49740 Binary files /dev/null and b/decoder_wave.png differ diff --git a/mult_table.png b/mult_table.png new file mode 100644 index 0000000..75de82f Binary files /dev/null and b/mult_table.png differ diff --git a/mult_wave.png b/mult_wave.png new file mode 100644 index 0000000..83ba0e5 Binary files /dev/null and b/mult_wave.png differ diff --git a/multiplexer.t.v b/multiplexer.t.v index fd475c4..055ee94 100644 --- a/multiplexer.t.v +++ b/multiplexer.t.v @@ -3,5 +3,30 @@ `include "multiplexer.v" module testMultiplexer (); - // Your test code here + reg address0, address1, in0, in1, in2, in3; + wire out; + + structuralMultiplexer mult (out, address0, address1, in0, in1, in2, in3); + + initial begin + $dumpfile("mult_trace.vcd"); + $dumpvars; + $display(" S0 S1 | in0 in1 in2 in3 | Out | Expected Output"); + address0=1'b0; address1=1'b0; in0=1'b0; in1=1'bX; in2=1'bX; in3=1'bX; #1000 + $display(" %b %b | %b %b %b %b | %b | False", address0, address1, in0, in1, in2, in3, out); + address0=1'b0; address1=1'b0; in0=1'b1; in1=1'bX; in2=1'bX; in3=1'bX; #1000 + $display(" %b %b | %b %b %b %b | %b | True", address0, address1, in0, in1, in2, in3, out); + address0=1'b0; address1=1'b1; in0=1'bX; in1=1'b0; in2=1'bX; in3=1'bX; #1000 + $display(" %b %b | %b %b %b %b | %b | False", address0, address1, in0, in1, in2, in3, out); + address0=1'b0; address1=1'b1; in0=1'bX; in1=1; in2=1'bX; in3=1'bX; #1000 + $display(" %b %b | %b %b %b %b | %b | True", address0, address1, in0, in1, in2, in3, out); + address0=1'b1; address1=1'b0; in0=1'bX; in1=1'bX; in2=1'b0; in3=1'bX; #1000 + $display(" %b %b | %b %b %b %b | %b | False", address0, address1, in0, in1, in2, in3, out); + address0=1'b1; address1=1'b0; in0=1'bX; in1=1'bX; in2=1'b1; in3=1'bX; #1000 + $display(" %b %b | %b %b %b %b | %b | True", address0, address1, in0, in1, in2, in3, out); + address0=1'b1; address1=1'b1; in0=1'bX; in1=1'bX; in2=1'bX; in3=1'b0; #1000 + $display(" %b %b | %b %b %b %b | %b | False", address0, address1, in0, in1, in2, in3, out); + address0=1'b1; address1=1'b1; in0=1'bX; in1=1'bX; in2=1'bX; in3=1'b1; #1000 + $display(" %b %b | %b %b %b %b | %b | True", address0, address1, in0, in1, in2, in3, out); + end endmodule diff --git a/multiplexer.v b/multiplexer.v index b05820f..8c76f44 100644 --- a/multiplexer.v +++ b/multiplexer.v @@ -1,5 +1,10 @@ // Multiplexer circuit +// define gates with delays +`define AND and #100 +`define OR or #100 +`define NOT not #100 + module behavioralMultiplexer ( output out, @@ -19,6 +24,30 @@ module structuralMultiplexer input address0, address1, input in0, in1, in2, in3 ); - // Your multiplexer code here + // First, set the selectors and their inverses + wire _address0, _address1; + `NOT invA0(_address0, address0); + `NOT invA1(_address1, address1); + + // Next, disregard half the inputs with address1 + wire MI0, MI1, MI2, MI3; + `AND maybeI0(MI0, _address1, in0); + `AND maybeI1(MI1, address1, in1); + `AND maybeI2(MI2, _address1, in2); + `AND maybeI3(MI3, address1, in3); + + // I0+I1, I2+I3 + wire I01, I23; + `OR i0or1(I01, MI0, MI1); + `OR i2or3(I23, MI2, MI3); + + // Next selector + wire M01, M23; + `AND maybe01(M01, _address0, I01); + `AND maybe23(M23, address0, I23); + + // Finally, OR them together for the result + `OR eithertrue(out, M01, M23); + endmodule diff --git a/results.md b/results.md new file mode 100644 index 0000000..7caff66 --- /dev/null +++ b/results.md @@ -0,0 +1,47 @@ +# Homework 2 +## Computer Architecture Fall 2017 +## Kaitlyn Keil + +### Multiplexer + +[Module here](https://github.com/KaitlynKeil/HW2/blob/master/multiplexer.v) + +[Test code here](https://github.com/KaitlynKeil/HW2/blob/master/multiplexer.t.v) + +Results: + +![Truth table results for a Multiplexer](https://github.com/KaitlynKeil/HW2/blob/master/mult_table.png "Multiplexer Truth Table Results") + +Wave results: + +The red indicates that it does not matter which state those inputs are in. + +![GTK-Wave results for a Multiplexer](https://github.com/KaitlynKeil/HW2/blob/master/mult_wave.png "Multiplexer GTK-Wave Results") + +### Decoder + +[Module here](https://github.com/KaitlynKeil/HW2/blob/master/decoder.v) + +[Test code here](https://github.com/KaitlynKeil/HW2/blob/master/decoder.t.v) + +Results: + +![Truth table results for a Decoder](https://github.com/KaitlynKeil/HW2/blob/master/decoder_table.png "Decoder Truth Table Results") + +Wave results: + +![GTK-Wave results for a Decoder](https://github.com/KaitlynKeil/HW2/blob/master/decoder_wave.png "Decoder GTK-Wave Results") + +### Full Adder + +[Module here](https://github.com/KaitlynKeil/HW2/blob/master/adder.v) + +[Test code here](https://github.com/KaitlynKeil/HW2/blob/master/adder.t.v) + +Results: + +![Truth table results for a Full Adder](https://github.com/KaitlynKeil/HW2/blob/master/adder_table.png "Full Adder Truth Table Results") + +Wave results: + +![GTK-Wave results for a Full Adder](https://github.com/KaitlynKeil/HW2/blob/master/adder_wave.png "Full Adder GTK-Wave Results")