diff --git a/adder.t.v b/adder.t.v
index 76109ed..d4db2cb 100644
--- a/adder.t.v
+++ b/adder.t.v
@@ -6,9 +6,28 @@ module testFullAdder();
     reg a, b, carryin;
     wire sum, carryout;
 
-    behavioralFullAdder adder (sum, carryout, a, b, carryin);
+    //behavioralFullAdder adder (sum, carryout, a, b, carryin);
+    structuralFullAdder adder (sum, carryout, a, b, carryin);
 
     initial begin
-        // Your test code here
+    	$dumpfile("adder.vcd");
+        $dumpvars(0, a, b, carryin, sum, carryout);
+        $display("A  B  Cin | Sum  Cout | Expected Output");
+    	a=0;b=0;carryin=0; #1000 
+    	$display("%b  %b  %b   | %b    %b    | 0 0", a, b, carryin, sum, carryout);
+    	a=0;b=0;carryin=1; #1000 
+    	$display("%b  %b  %b   | %b    %b    | 1 0", a, b, carryin, sum, carryout);
+    	a=0;b=1;carryin=0; #1000 
+    	$display("%b  %b  %b   | %b    %b    | 1 0", a, b, carryin, sum, carryout);
+    	a=0;b=1;carryin=1; #1000 
+    	$display("%b  %b  %b   | %b    %b    | 0 1", a, b, carryin, sum, carryout);
+    	a=1;b=0;carryin=0; #1000 
+    	$display("%b  %b  %b   | %b    %b    | 1 0", a, b, carryin, sum, carryout);
+    	a=1;b=0;carryin=1; #1000 
+    	$display("%b  %b  %b   | %b    %b    | 0 1", a, b, carryin, sum, carryout);
+    	a=1;b=1;carryin=0; #1000 
+    	$display("%b  %b  %b   | %b    %b    | 0 1", a, b, carryin, sum, carryout);
+    	a=1;b=1;carryin=1; #1000 
+    	$display("%b  %b  %b   | %b    %b    | 1 1", a, b, carryin, sum, carryout);
     end
 endmodule
diff --git a/adder.v b/adder.v
index d21f7e4..e4332f0 100644
--- a/adder.v
+++ b/adder.v
@@ -1,4 +1,8 @@
 // Adder circuit
+`define AND and #50
+`define OR or #50
+`define NOT not #50
+`define XOR xor #50
 
 module behavioralFullAdder
 (
@@ -20,5 +24,13 @@ module structuralFullAdder
     input b, 
     input carryin
 );
-    // Your adder code here
+    wire AxorB;
+    wire CAxorB;
+    wire AB;
+    `XOR(AxorB, a, b);
+    `XOR(sum, AxorB, carryin);
+    `AND(AB, a, b);
+    `AND(CAxorB, carryin, AxorB);
+    `OR(carryout, AB, CAxorB);
+
 endmodule
diff --git a/decoder.t.v b/decoder.t.v
index e0e925f..3ee3bad 100644
--- a/decoder.t.v
+++ b/decoder.t.v
@@ -7,27 +7,29 @@ module testDecoder ();
     reg enable;
     wire out0,out1,out2,out3;
 
-    behavioralDecoder decoder (out0,out1,out2,out3,addr0,addr1,enable);
-    //structuralDecoder decoder (out0,out1,out2,out3,addr0,addr1,enable); // Swap after testing
+    //behavioralDecoder decoder (out0,out1,out2,out3,addr0,addr1,enable);
+    structuralDecoder decoder (out0,out1,out2,out3,addr0,addr1,enable); // Swap after testing
 
     initial begin
-    $display("En A0 A1| O0 O1 O2 O3 | Expected Output");
-    enable=0;addr0=0;addr1=0; #1000 
-    $display("%b  %b  %b |  %b  %b  %b  %b | All false", enable, addr0, addr1, out0, out1, out2, out3);
-    enable=0;addr0=1;addr1=0; #1000
-    $display("%b  %b  %b |  %b  %b  %b  %b | All false", enable, addr0, addr1, out0, out1, out2, out3);
-    enable=0;addr0=0;addr1=1; #1000 
-    $display("%b  %b  %b |  %b  %b  %b  %b | All false", enable, addr0, addr1, out0, out1, out2, out3);
-    enable=0;addr0=1;addr1=1; #1000 
-    $display("%b  %b  %b |  %b  %b  %b  %b | All false", enable, addr0, addr1, out0, out1, out2, out3);
-    enable=1;addr0=0;addr1=0; #1000 
-    $display("%b  %b  %b |  %b  %b  %b  %b | O0 Only", enable, addr0, addr1, out0, out1, out2, out3);
-    enable=1;addr0=1;addr1=0; #1000 
-    $display("%b  %b  %b |  %b  %b  %b  %b | O1 Only", enable, addr0, addr1, out0, out1, out2, out3);
-    enable=1;addr0=0;addr1=1; #1000 
-    $display("%b  %b  %b |  %b  %b  %b  %b | O2 Only", enable, addr0, addr1, out0, out1, out2, out3);
-    enable=1;addr0=1;addr1=1; #1000 
-    $display("%b  %b  %b |  %b  %b  %b  %b | O3 Only", enable, addr0, addr1, out0, out1, out2, out3);
+        $dumpfile("decoder.vcd");
+        $dumpvars(0, addr0, addr1, out0, out1, out2, out3, enable);
+        $display("En A0 A1| O0 O1 O2 O3 | Expected Output");
+        enable=0;addr0=0;addr1=0; #1000 
+        $display("%b  %b  %b |  %b  %b  %b  %b | All false", enable, addr0, addr1, out0, out1, out2, out3);
+        enable=0;addr0=1;addr1=0; #1000
+        $display("%b  %b  %b |  %b  %b  %b  %b | All false", enable, addr0, addr1, out0, out1, out2, out3);
+        enable=0;addr0=0;addr1=1; #1000 
+        $display("%b  %b  %b |  %b  %b  %b  %b | All false", enable, addr0, addr1, out0, out1, out2, out3);
+        enable=0;addr0=1;addr1=1; #1000 
+        $display("%b  %b  %b |  %b  %b  %b  %b | All false", enable, addr0, addr1, out0, out1, out2, out3);
+        enable=1;addr0=0;addr1=0; #1000 
+        $display("%b  %b  %b |  %b  %b  %b  %b | O0 Only", enable, addr0, addr1, out0, out1, out2, out3);
+        enable=1;addr0=1;addr1=0; #1000 
+        $display("%b  %b  %b |  %b  %b  %b  %b | O1 Only", enable, addr0, addr1, out0, out1, out2, out3);
+        enable=1;addr0=0;addr1=1; #1000 
+        $display("%b  %b  %b |  %b  %b  %b  %b | O2 Only", enable, addr0, addr1, out0, out1, out2, out3);
+        enable=1;addr0=1;addr1=1; #1000 
+        $display("%b  %b  %b |  %b  %b  %b  %b | O3 Only", enable, addr0, addr1, out0, out1, out2, out3);
     end
 
 endmodule
diff --git a/decoder.v b/decoder.v
index 17836e0..f7524ce 100644
--- a/decoder.v
+++ b/decoder.v
@@ -1,4 +1,8 @@
 // Decoder circuit
+`define AND and #50
+`define OR or #50
+`define NOT not #50
+`define XOR xor #50
 
 module behavioralDecoder
 (
@@ -14,9 +18,23 @@ endmodule
 module structuralDecoder
 (
     output out0, out1, out2, out3,
-    input address0, address1,
+    input A, B,
     input enable
 );
-    // Your decoder code here
-endmodule
-
+	wire nA;
+	wire nB;
+	wire AB;
+	wire nAB;
+	wire AnB;
+	wire nAnB;
+    `NOT(nA, A);
+    `NOT(nB, B);
+    `AND(nAnB, nA, nB);
+    `AND(AnB, A, nB);
+    `AND(nAB, nA, B);
+    `AND(AB, A, B);
+    `AND(out0, enable, nAnB);
+    `AND(out1, enable, AnB);
+    `AND(out2, enable, nAB);
+    `AND(out3, enable, AB);
+endmodule
\ No newline at end of file
diff --git a/hw_writeup.pdf b/hw_writeup.pdf
new file mode 100644
index 0000000..63f7994
Binary files /dev/null and b/hw_writeup.pdf differ
diff --git a/multiplexer.t.v b/multiplexer.t.v
index fd475c4..3e63c83 100644
--- a/multiplexer.t.v
+++ b/multiplexer.t.v
@@ -3,5 +3,25 @@
 `include "multiplexer.v"
 
 module testMultiplexer ();
-  // Your test code here
+  reg in0, in1, in2, in3;
+  reg addr0, addr1;
+  wire out;
+
+  //behavioralMultiplexer mux(out, addr0, addr1, in0, in1, in2, in3);
+  structuralMultiplexer mux(in0, in1, in2, in3, addr0, addr1, out);
+
+  initial begin
+    $dumpfile("multiplexer.vcd");
+    $dumpvars(0, in0, in1, in2, in3, addr0, addr1, out);
+    $display("A0 A 1| in0 in1 in2 in3 | Out | Expected Output");
+    in0=1;in1=0;in2=0;in3=0;addr0=0;addr1=0; #1000 
+    $display("%b  %b  |  %b   %b   %b   %b  |  %b  | O1 Only", addr0, addr1, in0, in1, in2, in3, out);
+    in0=0;in1=1;in2=0;in3=0;addr0=1;addr1=0; #1000 
+    $display("%b  %b  |  %b   %b   %b   %b  |  %b  | O2 Only", addr0, addr1, in0, in1, in2, in3, out);
+    in0=0;in1=0;in2=1;in3=0;addr0=0;addr1=1; #1000 
+    $display("%b  %b  |  %b   %b   %b   %b  |  %b  | O3 Only", addr0, addr1, in0, in1, in2, in3, out);
+    in0=0;in1=0;in2=0;in3=1;addr0=1;addr1=1; #1000 
+    $display("%b  %b  |  %b   %b   %b   %b  |  %b  | O4 Only", addr0, addr1, in0, in1, in2, in3, out);
+    end
+
 endmodule
diff --git a/multiplexer.v b/multiplexer.v
index b05820f..66dd34c 100644
--- a/multiplexer.v
+++ b/multiplexer.v
@@ -15,10 +15,33 @@ endmodule
 
 module structuralMultiplexer
 (
-    output out,
-    input address0, address1,
-    input in0, in1, in2, in3
+    input in0, in1, in2, in3,
+    input A, B,
+    output out
 );
-    // Your multiplexer code here
+    wire nA;
+    wire nB;
+    wire AB;
+    wire nAB;
+    wire AnB;
+    wire nAnB;
+    wire or1;
+    wire or2;
+    wire o0, o1, o2, o3;
+    not(nA, A);
+    not(nB, B);
+    and(nAnB, nA, nB);
+    and(AnB, A, nB);
+    and(nAB, nA, B);
+    and(AB, A, B);
+    and(o0, in0, nAnB);
+    and(o1, in1, AnB);
+    and(o2, in2, nAB);
+    and(o3, in3, AB);
+
+    or(or1, o0, o1);
+    or(or2, o2, o3);
+    or(out, or1, or2);
+
 endmodule