diff --git a/Writeup.pdf b/Writeup.pdf
new file mode 100644
index 0000000..4670b1c
Binary files /dev/null and b/Writeup.pdf differ
diff --git a/adder b/adder
new file mode 100755
index 0000000..105cee9
--- /dev/null
+++ b/adder
@@ -0,0 +1,153 @@
+#! /usr/bin/vvp
+:ivl_version "0.9.7 " "(v0_9_7)";
+:vpi_time_precision - 12;
+:vpi_module "system";
+:vpi_module "v2005_math";
+:vpi_module "va_math";
+S_0xa42730 .scope module, "testFullAdder" "testFullAdder" 2 5;
+ .timescale -9 -12;
+v0xa9ee70_0 .net "Cout", 0 0, L_0xaa0040; 1 drivers
+v0xa9ef20_0 .var "a", 0 0;
+v0xa9efa0_0 .var "b", 0 0;
+v0xa9f070_0 .var "carryin", 0 0;
+v0xa9f140_0 .net "carryout", 0 0, L_0xa9f2c0; 1 drivers
+v0xa9f1c0_0 .net "structsum", 0 0, L_0xa9fdd0; 1 drivers
+v0xa9f240_0 .net "sum", 0 0, L_0xa9f3b0; 1 drivers
+S_0xa9e480 .scope module, "adder" "behavioralFullAdder" 2 10, 3 10, S_0xa42730;
+ .timescale -9 -12;
+v0xa9e570_0 .net *"_s10", 0 0, C4<0>; 1 drivers
+v0xa9e630_0 .net *"_s11", 1 0, L_0xa9f7b0; 1 drivers
+v0xa9e6d0_0 .net *"_s13", 1 0, L_0xa9f9c0; 1 drivers
+v0xa9e770_0 .net *"_s16", 0 0, C4<0>; 1 drivers
+v0xa9e7f0_0 .net *"_s17", 1 0, L_0xa9fb30; 1 drivers
+v0xa9e890_0 .net *"_s3", 1 0, L_0xa9f4f0; 1 drivers
+v0xa9e930_0 .net *"_s6", 0 0, C4<0>; 1 drivers
+v0xa9e9d0_0 .net *"_s7", 1 0, L_0xa9f620; 1 drivers
+v0xa9eac0_0 .net "a", 0 0, v0xa9ef20_0; 1 drivers
+v0xa9eb40_0 .net "b", 0 0, v0xa9efa0_0; 1 drivers
+v0xa9ec50_0 .net "carryin", 0 0, v0xa9f070_0; 1 drivers
+v0xa9ed00_0 .alias "carryout", 0 0, v0xa9f140_0;
+v0xa9edf0_0 .alias "sum", 0 0, v0xa9f240_0;
+L_0xa9f2c0 .part L_0xa9fb30, 1, 1;
+L_0xa9f3b0 .part L_0xa9fb30, 0, 1;
+L_0xa9f4f0 .concat [ 1 1 0 0], v0xa9ef20_0, C4<0>;
+L_0xa9f620 .concat [ 1 1 0 0], v0xa9efa0_0, C4<0>;
+L_0xa9f7b0 .arith/sum 2, L_0xa9f4f0, L_0xa9f620;
+L_0xa9f9c0 .concat [ 1 1 0 0], v0xa9f070_0, C4<0>;
+L_0xa9fb30 .arith/sum 2, L_0xa9f7b0, L_0xa9f9c0;
+S_0xa42820 .scope module, "structural" "structuralFullAdder" 2 12, 3 22, S_0xa42730;
+ .timescale -9 -12;
+L_0xa9ebc0/d .functor XOR 1, v0xa9ef20_0, v0xa9efa0_0, C4<0>, C4<0>;
+L_0xa9ebc0 .delay (50000,50000,50000) L_0xa9ebc0/d;
+L_0xa9fdd0/d .functor XOR 1, L_0xa9ebc0, v0xa9f070_0, C4<0>, C4<0>;
+L_0xa9fdd0 .delay (50000,50000,50000) L_0xa9fdd0/d;
+L_0xa9ff00/d .functor AND 1, v0xa9ef20_0, v0xa9efa0_0, C4<1>, C4<1>;
+L_0xa9ff00 .delay (50000,50000,50000) L_0xa9ff00/d;
+L_0xa9ffa0/d .functor AND 1, v0xa9f070_0, L_0xa9ebc0, C4<1>, C4<1>;
+L_0xa9ffa0 .delay (50000,50000,50000) L_0xa9ffa0/d;
+L_0xaa0040/d .functor OR 1, L_0xa9ff00, L_0xa9ffa0, C4<0>, C4<0>;
+L_0xaa0040 .delay (50000,50000,50000) L_0xaa0040/d;
+v0xa71af0_0 .net "AandB", 0 0, L_0xa9ff00; 1 drivers
+v0xa9df80_0 .net "AxorB", 0 0, L_0xa9ebc0; 1 drivers
+v0xa9e020_0 .net "CAxorB", 0 0, L_0xa9ffa0; 1 drivers
+v0xa9e0c0_0 .alias "Cout", 0 0, v0xa9ee70_0;
+v0xa9e170_0 .alias "a", 0 0, v0xa9eac0_0;
+v0xa9e210_0 .alias "b", 0 0, v0xa9eb40_0;
+v0xa9e2f0_0 .alias "carryin", 0 0, v0xa9ec50_0;
+v0xa9e390_0 .alias "structsum", 0 0, v0xa9f1c0_0;
+    .scope S_0xa42730;
+T_0 ;
+    %vpi_call 2 16 "$dumpfile", "adder.vcd";
+    %vpi_call 2 17 "$dumpvars";
+    %vpi_call 2 19 "$display", "Behavioral Full Adder";
+    %vpi_call 2 20 "$display", "A B CarryIn| Sum CarryOut | ExpectedSum ExpectedCarryOut";
+    %set/v v0xa9ef20_0, 0, 1;
+    %set/v v0xa9efa0_0, 0, 1;
+    %set/v v0xa9f070_0, 0, 1;
+    %delay 1000000, 0;
+    %vpi_call 2 22 "$display", "%b  %b  %b | %b  %b  | 0 0", v0xa9ef20_0, v0xa9efa0_0, v0xa9f070_0, v0xa9f240_0, v0xa9f140_0;
+    %set/v v0xa9ef20_0, 0, 1;
+    %set/v v0xa9efa0_0, 0, 1;
+    %set/v v0xa9f070_0, 1, 1;
+    %delay 1000000, 0;
+    %vpi_call 2 24 "$display", "%b  %b  %b | %b  %b  | 1 0", v0xa9ef20_0, v0xa9efa0_0, v0xa9f070_0, v0xa9f240_0, v0xa9f140_0;
+    %set/v v0xa9ef20_0, 0, 1;
+    %set/v v0xa9efa0_0, 1, 1;
+    %set/v v0xa9f070_0, 0, 1;
+    %delay 1000000, 0;
+    %vpi_call 2 26 "$display", "%b  %b  %b | %b  %b  | 1 0", v0xa9ef20_0, v0xa9efa0_0, v0xa9f070_0, v0xa9f240_0, v0xa9f140_0;
+    %set/v v0xa9ef20_0, 0, 1;
+    %set/v v0xa9efa0_0, 1, 1;
+    %set/v v0xa9f070_0, 1, 1;
+    %delay 1000000, 0;
+    %vpi_call 2 28 "$display", "%b  %b  %b | %b  %b  | 0 1", v0xa9ef20_0, v0xa9efa0_0, v0xa9f070_0, v0xa9f240_0, v0xa9f140_0;
+    %set/v v0xa9ef20_0, 1, 1;
+    %set/v v0xa9efa0_0, 0, 1;
+    %set/v v0xa9f070_0, 0, 1;
+    %delay 1000000, 0;
+    %vpi_call 2 30 "$display", "%b  %b  %b | %b  %b  | 1 0", v0xa9ef20_0, v0xa9efa0_0, v0xa9f070_0, v0xa9f240_0, v0xa9f140_0;
+    %set/v v0xa9ef20_0, 1, 1;
+    %set/v v0xa9efa0_0, 0, 1;
+    %set/v v0xa9f070_0, 1, 1;
+    %delay 1000000, 0;
+    %vpi_call 2 32 "$display", "%b  %b  %b | %b  %b  | 0 1", v0xa9ef20_0, v0xa9efa0_0, v0xa9f070_0, v0xa9f240_0, v0xa9f140_0;
+    %set/v v0xa9ef20_0, 1, 1;
+    %set/v v0xa9efa0_0, 1, 1;
+    %set/v v0xa9f070_0, 0, 1;
+    %delay 1000000, 0;
+    %vpi_call 2 34 "$display", "%b  %b  %b | %b  %b  | 0 1", v0xa9ef20_0, v0xa9efa0_0, v0xa9f070_0, v0xa9f240_0, v0xa9f140_0;
+    %set/v v0xa9ef20_0, 1, 1;
+    %set/v v0xa9efa0_0, 1, 1;
+    %set/v v0xa9f070_0, 1, 1;
+    %delay 1000000, 0;
+    %vpi_call 2 36 "$display", "%b  %b  %b | %b  %b  | 1 1", v0xa9ef20_0, v0xa9efa0_0, v0xa9f070_0, v0xa9f240_0, v0xa9f140_0;
+    %vpi_call 2 38 "$display", "Structural Full Adder";
+    %vpi_call 2 39 "$display", "A B CarryIn| Sum CarryOut | ExpectedSum ExpectedCarryOut";
+    %set/v v0xa9ef20_0, 0, 1;
+    %set/v v0xa9efa0_0, 0, 1;
+    %set/v v0xa9f070_0, 0, 1;
+    %delay 1000000, 0;
+    %vpi_call 2 41 "$display", "%b  %b  %b | %b  %b  | 0 0", v0xa9ef20_0, v0xa9efa0_0, v0xa9f070_0, v0xa9f1c0_0, v0xa9ee70_0;
+    %set/v v0xa9ef20_0, 0, 1;
+    %set/v v0xa9efa0_0, 0, 1;
+    %set/v v0xa9f070_0, 1, 1;
+    %delay 1000000, 0;
+    %vpi_call 2 43 "$display", "%b  %b  %b | %b  %b  | 1 0", v0xa9ef20_0, v0xa9efa0_0, v0xa9f070_0, v0xa9f1c0_0, v0xa9ee70_0;
+    %set/v v0xa9ef20_0, 0, 1;
+    %set/v v0xa9efa0_0, 1, 1;
+    %set/v v0xa9f070_0, 0, 1;
+    %delay 1000000, 0;
+    %vpi_call 2 45 "$display", "%b  %b  %b | %b  %b  | 1 0", v0xa9ef20_0, v0xa9efa0_0, v0xa9f070_0, v0xa9f1c0_0, v0xa9ee70_0;
+    %set/v v0xa9ef20_0, 0, 1;
+    %set/v v0xa9efa0_0, 1, 1;
+    %set/v v0xa9f070_0, 1, 1;
+    %delay 1000000, 0;
+    %vpi_call 2 47 "$display", "%b  %b  %b | %b  %b  | 0 1", v0xa9ef20_0, v0xa9efa0_0, v0xa9f070_0, v0xa9f1c0_0, v0xa9ee70_0;
+    %set/v v0xa9ef20_0, 1, 1;
+    %set/v v0xa9efa0_0, 0, 1;
+    %set/v v0xa9f070_0, 0, 1;
+    %delay 1000000, 0;
+    %vpi_call 2 49 "$display", "%b  %b  %b | %b  %b  | 1 0", v0xa9ef20_0, v0xa9efa0_0, v0xa9f070_0, v0xa9f1c0_0, v0xa9ee70_0;
+    %set/v v0xa9ef20_0, 1, 1;
+    %set/v v0xa9efa0_0, 0, 1;
+    %set/v v0xa9f070_0, 1, 1;
+    %delay 1000000, 0;
+    %vpi_call 2 51 "$display", "%b  %b  %b | %b  %b  | 0 1", v0xa9ef20_0, v0xa9efa0_0, v0xa9f070_0, v0xa9f1c0_0, v0xa9ee70_0;
+    %set/v v0xa9ef20_0, 1, 1;
+    %set/v v0xa9efa0_0, 1, 1;
+    %set/v v0xa9f070_0, 0, 1;
+    %delay 1000000, 0;
+    %vpi_call 2 53 "$display", "%b  %b  %b | %b  %b  | 0 1", v0xa9ef20_0, v0xa9efa0_0, v0xa9f070_0, v0xa9f1c0_0, v0xa9ee70_0;
+    %set/v v0xa9ef20_0, 1, 1;
+    %set/v v0xa9efa0_0, 1, 1;
+    %set/v v0xa9f070_0, 1, 1;
+    %delay 1000000, 0;
+    %vpi_call 2 55 "$display", "%b  %b  %b | %b  %b  | 1 1", v0xa9ef20_0, v0xa9efa0_0, v0xa9f070_0, v0xa9f1c0_0, v0xa9ee70_0;
+    %end;
+    .thread T_0;
+# The file index is used to find the file name in the following table.
+:file_names 4;
+    "N/A";
+    "<interactive>";
+    "adder.t.v";
+    "./adder.v";
diff --git a/adder.t.v b/adder.t.v
index 76109ed..8c505a2 100644
--- a/adder.t.v
+++ b/adder.t.v
@@ -1,14 +1,58 @@
-// Adder testbench
-`timescale 1 ns / 1 ps
-`include "adder.v"
-
-module testFullAdder();
-    reg a, b, carryin;
-    wire sum, carryout;
-
-    behavioralFullAdder adder (sum, carryout, a, b, carryin);
-
-    initial begin
-        // Your test code here
-    end
-endmodule
+// Adder testbench
+`timescale 1 ns / 1 ps
+`include "adder.v"
+
+module testFullAdder();
+    reg a, b, carryin;
+    wire sum, carryout;
+	wire structsum, AxorB, AandB, CAxorB, Cout;
+
+	behavioralFullAdder adder (sum, carryout, a, b, carryin);
+
+	structuralFullAdder structural(a, b, carryin, structsum, Cout);
+
+    initial begin
+
+	$dumpfile("adder.vcd");
+	$dumpvars();
+
+	$display("Behavioral Full Adder");
+    $display("A B CarryIn| Sum CarryOut | ExpectedSum ExpectedCarryOut");
+    a=0; b = 0; carryin = 0; #1000 
+    $display("%b  %b  %b | %b  %b  | 0 0", a, b, carryin, sum, carryout);
+    a=0; b = 0; carryin = 1; #1000 
+    $display("%b  %b  %b | %b  %b  | 1 0", a, b, carryin, sum, carryout);
+    a=0; b = 1; carryin = 0; #1000 
+    $display("%b  %b  %b | %b  %b  | 1 0", a, b, carryin, sum, carryout);
+    a=0; b = 1; carryin = 1; #1000 
+    $display("%b  %b  %b | %b  %b  | 0 1", a, b, carryin, sum, carryout);
+    a=1; b = 0; carryin = 0; #1000 
+    $display("%b  %b  %b | %b  %b  | 1 0", a, b, carryin, sum, carryout);
+    a=1; b = 0; carryin = 1; #1000 
+    $display("%b  %b  %b | %b  %b  | 0 1", a, b, carryin, sum, carryout);
+    a=1; b = 1; carryin = 0; #1000 
+    $display("%b  %b  %b | %b  %b  | 0 1", a, b, carryin, sum, carryout);
+    a=1; b = 1; carryin = 1; #1000 
+    $display("%b  %b  %b | %b  %b  | 1 1", a, b, carryin, sum, carryout);
+
+	$display("Structural Full Adder");
+    $display("A B CarryIn| Sum CarryOut | ExpectedSum ExpectedCarryOut");
+    a=0; b = 0; carryin = 0; #1000 
+    $display("%b  %b  %b | %b  %b  | 0 0", a, b, carryin, structsum, Cout);
+    a=0; b = 0; carryin = 1; #1000 
+    $display("%b  %b  %b | %b  %b  | 1 0", a, b, carryin, structsum, Cout);
+    a=0; b = 1; carryin = 0; #1000 
+    $display("%b  %b  %b | %b  %b  | 1 0", a, b, carryin, structsum, Cout);
+    a=0; b = 1; carryin = 1; #1000 
+    $display("%b  %b  %b | %b  %b  | 0 1", a, b, carryin, structsum, Cout);
+    a=1; b = 0; carryin = 0; #1000 
+    $display("%b  %b  %b | %b  %b  | 1 0", a, b, carryin, structsum, Cout);
+    a=1; b = 0; carryin = 1; #1000 
+    $display("%b  %b  %b | %b  %b  | 0 1", a, b, carryin, structsum, Cout);
+    a=1; b = 1; carryin = 0; #1000 
+    $display("%b  %b  %b | %b  %b  | 0 1", a, b, carryin, structsum, Cout);
+    a=1; b = 1; carryin = 1; #1000 
+    $display("%b  %b  %b | %b  %b  | 1 1", a, b, carryin, structsum, Cout);
+
+    end
+endmodule
diff --git a/adder.v b/adder.v
index d21f7e4..8ebe411 100644
--- a/adder.v
+++ b/adder.v
@@ -1,24 +1,41 @@
-// Adder circuit
-
-module behavioralFullAdder
-(
-    output sum, 
-    output carryout,
-    input a, 
-    input b, 
-    input carryin
-);
-    // Uses concatenation operator and built-in '+'
-    assign {carryout, sum}=a+b+carryin;
-endmodule
-
-module structuralFullAdder
-(
-    output sum, 
-    output carryout,
-    input a, 
-    input b, 
-    input carryin
-);
-    // Your adder code here
-endmodule
+// Adder circuit
+// an adder is a type of snake!
+
+// Multiplexer circuit
+`define AND and #50
+`define OR or #50
+`define NOT not #50
+`define XOR xor #50
+
+module behavioralFullAdder
+(
+    output sum, 
+    output carryout,
+    input a, 
+    input b, 
+    input carryin
+);
+    // Uses concatenation operator and built-in '+'
+    assign {carryout, sum}=a+b+carryin;
+endmodule
+
+module structuralFullAdder
+(
+    input a, 
+    input b, 
+    input carryin,
+    output structsum, Cout
+);
+
+	wire AxorB;
+	wire AandB;
+	wire CAxorB;	
+
+	`XOR xorgate1(AxorB, a, b);
+	`XOR xorgate2(structsum, AxorB, carryin);
+
+	`AND andgate1(AandB, a, b);
+	`AND andgate2(CAxorB, carryin, AxorB);
+	`OR orgate1(Cout, AandB, CAxorB);	
+
+endmodule
diff --git a/adder.vcd b/adder.vcd
new file mode 100644
index 0000000..cf81f85
--- /dev/null
+++ b/adder.vcd
@@ -0,0 +1,210 @@
+$date
+	Wed Sep 20 23:47:10 2017
+$end
+$version
+	Icarus Verilog
+$end
+$timescale
+	1ps
+$end
+$scope module testFullAdder $end
+$var wire 1 ! Cout $end
+$var wire 1 " carryout $end
+$var wire 1 # structsum $end
+$var wire 1 $ sum $end
+$var reg 1 % a $end
+$var reg 1 & b $end
+$var reg 1 ' carryin $end
+$scope module adder $end
+$var wire 1 ( a $end
+$var wire 1 ) b $end
+$var wire 1 * carryin $end
+$var wire 1 " carryout $end
+$var wire 1 $ sum $end
+$upscope $end
+$scope module structural $end
+$var wire 1 + AandB $end
+$var wire 1 , AxorB $end
+$var wire 1 - CAxorB $end
+$var wire 1 ! Cout $end
+$var wire 1 ( a $end
+$var wire 1 ) b $end
+$var wire 1 * carryin $end
+$var wire 1 # structsum $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+#0
+$dumpvars
+z-
+z,
+z+
+0*
+0)
+0(
+0'
+0&
+0%
+0$
+x#
+0"
+x!
+$end
+#50000
+0-
+0+
+0,
+#100000
+0!
+0#
+#1000000
+1$
+1'
+1*
+#1050000
+1#
+#2000000
+0'
+0*
+1&
+1)
+#2050000
+0#
+1,
+#2100000
+1#
+#3000000
+0$
+1"
+1'
+1*
+#3050000
+0#
+1-
+#3100000
+1!
+#4000000
+0"
+1$
+0'
+0*
+0&
+0)
+1%
+1(
+#4050000
+1#
+0-
+#4100000
+0!
+#5000000
+0$
+1"
+1'
+1*
+#5050000
+0#
+1-
+#5100000
+1!
+#6000000
+0'
+0*
+1&
+1)
+#6050000
+1#
+0-
+0,
+1+
+#6100000
+0#
+#7000000
+1$
+1'
+1*
+#7050000
+1#
+#8000000
+0"
+0$
+0'
+0*
+0&
+0)
+0%
+0(
+#8050000
+0#
+0+
+#8100000
+0!
+#9000000
+1$
+1'
+1*
+#9050000
+1#
+#10000000
+0'
+0*
+1&
+1)
+#10050000
+0#
+1,
+#10100000
+1#
+#11000000
+0$
+1"
+1'
+1*
+#11050000
+0#
+1-
+#11100000
+1!
+#12000000
+0"
+1$
+0'
+0*
+0&
+0)
+1%
+1(
+#12050000
+1#
+0-
+#12100000
+0!
+#13000000
+0$
+1"
+1'
+1*
+#13050000
+0#
+1-
+#13100000
+1!
+#14000000
+0'
+0*
+1&
+1)
+#14050000
+1#
+0-
+0,
+1+
+#14100000
+0#
+#15000000
+1$
+1'
+1*
+#15050000
+1#
+#16000000
diff --git a/counter.vcd b/counter.vcd
new file mode 100644
index 0000000..9ae901e
--- /dev/null
+++ b/counter.vcd
@@ -0,0 +1,278 @@
+$date
+	Tue Sep 19 19:55:12 2017
+$end
+$version
+	Icarus Verilog
+$end
+$timescale
+	1ps
+$end
+$scope module testDecoder $end
+$var wire 1 ! A0A1 $end
+$var wire 1 " A0nA1 $end
+$var wire 1 # Sout0 $end
+$var wire 1 $ Sout1 $end
+$var wire 1 % Sout2 $end
+$var wire 1 & Sout3 $end
+$var wire 1 ' nA0A1 $end
+$var wire 1 ( nA0nA1 $end
+$var wire 1 ) naddress0 $end
+$var wire 1 * naddress1 $end
+$var wire 1 + out0 $end
+$var wire 1 , out1 $end
+$var wire 1 - out2 $end
+$var wire 1 . out3 $end
+$var reg 1 / addr0 $end
+$var reg 1 0 addr1 $end
+$var reg 1 1 enable $end
+$scope module decoder $end
+$var wire 1 2 address0 $end
+$var wire 1 3 address1 $end
+$var wire 1 4 enable $end
+$var wire 1 + out0 $end
+$var wire 1 , out1 $end
+$var wire 1 - out2 $end
+$var wire 1 . out3 $end
+$upscope $end
+$scope module structuraltest $end
+$var wire 1 ! A0A1 $end
+$var wire 1 " A0nA1 $end
+$var wire 1 # Sout0 $end
+$var wire 1 $ Sout1 $end
+$var wire 1 % Sout2 $end
+$var wire 1 & Sout3 $end
+$var wire 1 2 address0 $end
+$var wire 1 3 address1 $end
+$var wire 1 4 enable $end
+$var wire 1 ' nA0A1 $end
+$var wire 1 ( nA0nA1 $end
+$var wire 1 ) naddress0 $end
+$var wire 1 * naddress1 $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+#0
+$dumpvars
+04
+03
+02
+01
+00
+0/
+0.
+0-
+0,
+0+
+z*
+z)
+x(
+z'
+z&
+z%
+z$
+z#
+z"
+z!
+$end
+#50000
+0&
+0!
+0%
+0'
+0$
+0"
+0#
+1)
+1*
+#100000
+1(
+#1000000
+1/
+12
+#1050000
+0)
+1"
+#1100000
+0(
+#2000000
+10
+13
+0/
+02
+#2050000
+0*
+1)
+0"
+#2100000
+1'
+#3000000
+1/
+12
+#3050000
+0)
+1!
+#3100000
+0'
+#4000000
+1+
+00
+03
+0/
+02
+11
+14
+#4050000
+1*
+1)
+0!
+1&
+#4100000
+1(
+0&
+#4150000
+1#
+#5000000
+0+
+1,
+1/
+12
+#5050000
+0)
+1"
+#5100000
+0(
+1$
+#5150000
+0#
+#6000000
+1-
+0,
+10
+13
+0/
+02
+#6050000
+0*
+1)
+0"
+#6100000
+1'
+0$
+#6150000
+1%
+#7000000
+0-
+1.
+1/
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+#7050000
+0)
+1!
+#7100000
+0'
+1&
+#7150000
+0%
+#8000000
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+00
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+04
+#8050000
+1*
+1)
+0!
+0&
+#8100000
+1(
+#9000000
+1/
+12
+#9050000
+0)
+1"
+#9100000
+0(
+#10000000
+10
+13
+0/
+02
+#10050000
+0*
+1)
+0"
+#10100000
+1'
+#11000000
+1/
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+#11050000
+0)
+1!
+#11100000
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+#12000000
+1+
+00
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+11
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+#12050000
+1*
+1)
+0!
+1&
+#12100000
+1(
+0&
+#12150000
+1#
+#13000000
+0+
+1,
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+#13050000
+0)
+1"
+#13100000
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+1$
+#13150000
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+#14000000
+1-
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+#14050000
+0*
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+#14100000
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+#14150000
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+#15000000
+0-
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diff --git a/decoder b/decoder
new file mode 100755
index 0000000..25ba7d5
--- /dev/null
+++ b/decoder
@@ -0,0 +1,170 @@
+#! /usr/bin/vvp
+:ivl_version "0.9.7 " "(v0_9_7)";
+:vpi_time_precision - 12;
+:vpi_module "system";
+:vpi_module "v2005_math";
+:vpi_module "va_math";
+S_0x2378690 .scope module, "testDecoder" "testDecoder" 2 5;
+ .timescale -9 -12;
+v0x23da500_0 .net "Sout0", 0 0, L_0x23db740; 1 drivers
+v0x23da5d0_0 .net "Sout1", 0 0, L_0x23db960; 1 drivers
+v0x23da680_0 .net "Sout2", 0 0, L_0x23dbb80; 1 drivers
+v0x23da730_0 .net "Sout3", 0 0, L_0x23dbdb0; 1 drivers
+v0x23da810_0 .var "addr0", 0 0;
+v0x23da890_0 .var "addr1", 0 0;
+v0x23da960_0 .var "enable", 0 0;
+v0x23daa30_0 .net "out0", 0 0, L_0x23dafb0; 1 drivers
+v0x23dab00_0 .net "out1", 0 0, L_0x23daec0; 1 drivers
+v0x23dab80_0 .net "out2", 0 0, L_0x23dad80; 1 drivers
+v0x23dac60_0 .net "out3", 0 0, L_0x23dace0; 1 drivers
+S_0x23d9d90 .scope module, "decoder" "behavioralDecoder" 2 12, 3 7, S_0x2378690;
+ .timescale -9 -12;
+v0x23d9e80_0 .net *"_s11", 3 0, L_0x23db2b0; 1 drivers
+v0x23d9f40_0 .net *"_s5", 3 0, L_0x23db130; 1 drivers
+v0x23d9fe0_0 .net *"_s8", 2 0, C4<000>; 1 drivers
+v0x23da080_0 .net *"_s9", 1 0, L_0x23db1d0; 1 drivers
+v0x23da100_0 .net "address0", 0 0, v0x23da810_0; 1 drivers
+v0x23da1b0_0 .net "address1", 0 0, v0x23da890_0; 1 drivers
+v0x23da230_0 .net "enable", 0 0, v0x23da960_0; 1 drivers
+v0x23da2e0_0 .alias "out0", 0 0, v0x23daa30_0;
+v0x23da360_0 .alias "out1", 0 0, v0x23dab00_0;
+v0x23da3e0_0 .alias "out2", 0 0, v0x23dab80_0;
+v0x23da460_0 .alias "out3", 0 0, v0x23dac60_0;
+L_0x23dace0 .part L_0x23db2b0, 3, 1;
+L_0x23dad80 .part L_0x23db2b0, 2, 1;
+L_0x23daec0 .part L_0x23db2b0, 1, 1;
+L_0x23dafb0 .part L_0x23db2b0, 0, 1;
+L_0x23db130 .concat [ 1 3 0 0], v0x23da960_0, C4<000>;
+L_0x23db1d0 .concat [ 1 1 0 0], v0x23da810_0, v0x23da890_0;
+L_0x23db2b0 .shift/l 4, L_0x23db130, L_0x23db1d0;
+S_0x2378780 .scope module, "structuraltest" "structuralDecoder" 2 13, 3 18, S_0x2378690;
+ .timescale -9 -12;
+L_0x23db3f0/d .functor NOT 1, v0x23da810_0, C4<0>, C4<0>, C4<0>;
+L_0x23db3f0 .delay (50000,50000,50000) L_0x23db3f0/d;
+L_0x23db520/d .functor NOT 1, v0x23da890_0, C4<0>, C4<0>, C4<0>;
+L_0x23db520 .delay (50000,50000,50000) L_0x23db520/d;
+L_0x23db650/d .functor AND 1, L_0x23db3f0, L_0x23db520, C4<1>, C4<1>;
+L_0x23db650 .delay (50000,50000,50000) L_0x23db650/d;
+L_0x23db740/d .functor AND 1, v0x23da960_0, L_0x23db650, C4<1>, C4<1>;
+L_0x23db740 .delay (50000,50000,50000) L_0x23db740/d;
+L_0x23db8c0/d .functor AND 1, v0x23da810_0, L_0x23db520, C4<1>, C4<1>;
+L_0x23db8c0 .delay (50000,50000,50000) L_0x23db8c0/d;
+L_0x23db960/d .functor AND 1, v0x23da960_0, L_0x23db8c0, C4<1>, C4<1>;
+L_0x23db960 .delay (50000,50000,50000) L_0x23db960/d;
+L_0x23dbae0/d .functor AND 1, L_0x23db3f0, v0x23da890_0, C4<1>, C4<1>;
+L_0x23dbae0 .delay (50000,50000,50000) L_0x23dbae0/d;
+L_0x23dbb80/d .functor AND 1, v0x23da960_0, L_0x23dbae0, C4<1>, C4<1>;
+L_0x23dbb80 .delay (50000,50000,50000) L_0x23dbb80/d;
+L_0x23dbce0/d .functor AND 1, v0x23da810_0, v0x23da890_0, C4<1>, C4<1>;
+L_0x23dbce0 .delay (50000,50000,50000) L_0x23dbce0/d;
+L_0x23dbdb0/d .functor AND 1, v0x23da960_0, L_0x23dbce0, C4<1>, C4<1>;
+L_0x23dbdb0 .delay (50000,50000,50000) L_0x23dbdb0/d;
+v0x23aeec0_0 .net "A0A1", 0 0, L_0x23dbce0; 1 drivers
+v0x23d94a0_0 .net "A0nA1", 0 0, L_0x23db8c0; 1 drivers
+v0x23d9540_0 .alias "Sout0", 0 0, v0x23da500_0;
+v0x23d95e0_0 .alias "Sout1", 0 0, v0x23da5d0_0;
+v0x23d9690_0 .alias "Sout2", 0 0, v0x23da680_0;
+v0x23d9730_0 .alias "Sout3", 0 0, v0x23da730_0;
+v0x23d9810_0 .alias "address0", 0 0, v0x23da100_0;
+v0x23d98b0_0 .alias "address1", 0 0, v0x23da1b0_0;
+v0x23d99a0_0 .alias "enable", 0 0, v0x23da230_0;
+v0x23d9a40_0 .net "nA0A1", 0 0, L_0x23dbae0; 1 drivers
+v0x23d9b40_0 .net "nA0nA1", 0 0, L_0x23db650; 1 drivers
+v0x23d9be0_0 .net "naddress0", 0 0, L_0x23db3f0; 1 drivers
+v0x23d9cf0_0 .net "naddress1", 0 0, L_0x23db520; 1 drivers
+    .scope S_0x2378690;
+T_0 ;
+    %vpi_call 2 17 "$dumpfile", "decoder.vcd";
+    %vpi_call 2 18 "$dumpvars";
+    %vpi_call 2 20 "$display", "Behavioral Decoder";
+    %vpi_call 2 21 "$display", "En A0 A1| O0 O1 O2 O3 | Expected Output";
+    %set/v v0x23da960_0, 0, 1;
+    %set/v v0x23da810_0, 0, 1;
+    %set/v v0x23da890_0, 0, 1;
+    %delay 1000000, 0;
+    %vpi_call 2 23 "$display", "%b  %b  %b |  %b  %b  %b  %b | All false", v0x23da960_0, v0x23da810_0, v0x23da890_0, v0x23daa30_0, v0x23dab00_0, v0x23dab80_0, v0x23dac60_0;
+    %set/v v0x23da960_0, 0, 1;
+    %set/v v0x23da810_0, 1, 1;
+    %set/v v0x23da890_0, 0, 1;
+    %delay 1000000, 0;
+    %vpi_call 2 25 "$display", "%b  %b  %b |  %b  %b  %b  %b | All false", v0x23da960_0, v0x23da810_0, v0x23da890_0, v0x23daa30_0, v0x23dab00_0, v0x23dab80_0, v0x23dac60_0;
+    %set/v v0x23da960_0, 0, 1;
+    %set/v v0x23da810_0, 0, 1;
+    %set/v v0x23da890_0, 1, 1;
+    %delay 1000000, 0;
+    %vpi_call 2 27 "$display", "%b  %b  %b |  %b  %b  %b  %b | All false", v0x23da960_0, v0x23da810_0, v0x23da890_0, v0x23daa30_0, v0x23dab00_0, v0x23dab80_0, v0x23dac60_0;
+    %set/v v0x23da960_0, 0, 1;
+    %set/v v0x23da810_0, 1, 1;
+    %set/v v0x23da890_0, 1, 1;
+    %delay 1000000, 0;
+    %vpi_call 2 29 "$display", "%b  %b  %b |  %b  %b  %b  %b | All false", v0x23da960_0, v0x23da810_0, v0x23da890_0, v0x23daa30_0, v0x23dab00_0, v0x23dab80_0, v0x23dac60_0;
+    %set/v v0x23da960_0, 1, 1;
+    %set/v v0x23da810_0, 0, 1;
+    %set/v v0x23da890_0, 0, 1;
+    %delay 1000000, 0;
+    %vpi_call 2 31 "$display", "%b  %b  %b |  %b  %b  %b  %b | O0 Only", v0x23da960_0, v0x23da810_0, v0x23da890_0, v0x23daa30_0, v0x23dab00_0, v0x23dab80_0, v0x23dac60_0;
+    %set/v v0x23da960_0, 1, 1;
+    %set/v v0x23da810_0, 1, 1;
+    %set/v v0x23da890_0, 0, 1;
+    %delay 1000000, 0;
+    %vpi_call 2 33 "$display", "%b  %b  %b |  %b  %b  %b  %b | O1 Only", v0x23da960_0, v0x23da810_0, v0x23da890_0, v0x23daa30_0, v0x23dab00_0, v0x23dab80_0, v0x23dac60_0;
+    %set/v v0x23da960_0, 1, 1;
+    %set/v v0x23da810_0, 0, 1;
+    %set/v v0x23da890_0, 1, 1;
+    %delay 1000000, 0;
+    %vpi_call 2 35 "$display", "%b  %b  %b |  %b  %b  %b  %b | O2 Only", v0x23da960_0, v0x23da810_0, v0x23da890_0, v0x23daa30_0, v0x23dab00_0, v0x23dab80_0, v0x23dac60_0;
+    %set/v v0x23da960_0, 1, 1;
+    %set/v v0x23da810_0, 1, 1;
+    %set/v v0x23da890_0, 1, 1;
+    %delay 1000000, 0;
+    %vpi_call 2 37 "$display", "%b  %b  %b |  %b  %b  %b  %b | O3 Only", v0x23da960_0, v0x23da810_0, v0x23da890_0, v0x23daa30_0, v0x23dab00_0, v0x23dab80_0, v0x23dac60_0;
+    %vpi_call 2 39 "$display", "Structural Decoder";
+    %vpi_call 2 40 "$display", "En A0 A1| O0 O1 O2 O3 | Expected Output";
+    %set/v v0x23da960_0, 0, 1;
+    %set/v v0x23da810_0, 0, 1;
+    %set/v v0x23da890_0, 0, 1;
+    %delay 1000000, 0;
+    %vpi_call 2 42 "$display", "%b  %b  %b |  %b  %b  %b  %b | All false", v0x23da960_0, v0x23da810_0, v0x23da890_0, v0x23da500_0, v0x23da5d0_0, v0x23da680_0, v0x23da730_0;
+    %set/v v0x23da960_0, 0, 1;
+    %set/v v0x23da810_0, 1, 1;
+    %set/v v0x23da890_0, 0, 1;
+    %delay 1000000, 0;
+    %vpi_call 2 44 "$display", "%b  %b  %b |  %b  %b  %b  %b | All false", v0x23da960_0, v0x23da810_0, v0x23da890_0, v0x23da500_0, v0x23da5d0_0, v0x23da680_0, v0x23da730_0;
+    %set/v v0x23da960_0, 0, 1;
+    %set/v v0x23da810_0, 0, 1;
+    %set/v v0x23da890_0, 1, 1;
+    %delay 1000000, 0;
+    %vpi_call 2 46 "$display", "%b  %b  %b |  %b  %b  %b  %b | All false", v0x23da960_0, v0x23da810_0, v0x23da890_0, v0x23da500_0, v0x23da5d0_0, v0x23da680_0, v0x23da730_0;
+    %set/v v0x23da960_0, 0, 1;
+    %set/v v0x23da810_0, 1, 1;
+    %set/v v0x23da890_0, 1, 1;
+    %delay 1000000, 0;
+    %vpi_call 2 48 "$display", "%b  %b  %b |  %b  %b  %b  %b | All false", v0x23da960_0, v0x23da810_0, v0x23da890_0, v0x23da500_0, v0x23da5d0_0, v0x23da680_0, v0x23da730_0;
+    %set/v v0x23da960_0, 1, 1;
+    %set/v v0x23da810_0, 0, 1;
+    %set/v v0x23da890_0, 0, 1;
+    %delay 1000000, 0;
+    %vpi_call 2 50 "$display", "%b  %b  %b |  %b  %b  %b  %b | O0 Only", v0x23da960_0, v0x23da810_0, v0x23da890_0, v0x23da500_0, v0x23da5d0_0, v0x23da680_0, v0x23da730_0;
+    %set/v v0x23da960_0, 1, 1;
+    %set/v v0x23da810_0, 1, 1;
+    %set/v v0x23da890_0, 0, 1;
+    %delay 1000000, 0;
+    %vpi_call 2 52 "$display", "%b  %b  %b |  %b  %b  %b  %b | O1 Only", v0x23da960_0, v0x23da810_0, v0x23da890_0, v0x23da500_0, v0x23da5d0_0, v0x23da680_0, v0x23da730_0;
+    %set/v v0x23da960_0, 1, 1;
+    %set/v v0x23da810_0, 0, 1;
+    %set/v v0x23da890_0, 1, 1;
+    %delay 1000000, 0;
+    %vpi_call 2 54 "$display", "%b  %b  %b |  %b  %b  %b  %b | O2 Only", v0x23da960_0, v0x23da810_0, v0x23da890_0, v0x23da500_0, v0x23da5d0_0, v0x23da680_0, v0x23da730_0;
+    %set/v v0x23da960_0, 1, 1;
+    %set/v v0x23da810_0, 1, 1;
+    %set/v v0x23da890_0, 1, 1;
+    %delay 1000000, 0;
+    %vpi_call 2 56 "$display", "%b  %b  %b |  %b  %b  %b  %b | O3 Only", v0x23da960_0, v0x23da810_0, v0x23da890_0, v0x23da500_0, v0x23da5d0_0, v0x23da680_0, v0x23da730_0;
+    %end;
+    .thread T_0;
+# The file index is used to find the file name in the following table.
+:file_names 4;
+    "N/A";
+    "<interactive>";
+    "decoder.t.v";
+    "./decoder.v";
diff --git a/decoder.t.v b/decoder.t.v
index e0e925f..9a579e6 100644
--- a/decoder.t.v
+++ b/decoder.t.v
@@ -1,33 +1,58 @@
-// Decoder testbench
-`timescale 1 ns / 1 ps
-`include "decoder.v"
-
-module testDecoder (); 
-    reg addr0, addr1;
-    reg enable;
-    wire out0,out1,out2,out3;
-
-    behavioralDecoder decoder (out0,out1,out2,out3,addr0,addr1,enable);
-    //structuralDecoder decoder (out0,out1,out2,out3,addr0,addr1,enable); // Swap after testing
-
-    initial begin
-    $display("En A0 A1| O0 O1 O2 O3 | Expected Output");
-    enable=0;addr0=0;addr1=0; #1000 
-    $display("%b  %b  %b |  %b  %b  %b  %b | All false", enable, addr0, addr1, out0, out1, out2, out3);
-    enable=0;addr0=1;addr1=0; #1000
-    $display("%b  %b  %b |  %b  %b  %b  %b | All false", enable, addr0, addr1, out0, out1, out2, out3);
-    enable=0;addr0=0;addr1=1; #1000 
-    $display("%b  %b  %b |  %b  %b  %b  %b | All false", enable, addr0, addr1, out0, out1, out2, out3);
-    enable=0;addr0=1;addr1=1; #1000 
-    $display("%b  %b  %b |  %b  %b  %b  %b | All false", enable, addr0, addr1, out0, out1, out2, out3);
-    enable=1;addr0=0;addr1=0; #1000 
-    $display("%b  %b  %b |  %b  %b  %b  %b | O0 Only", enable, addr0, addr1, out0, out1, out2, out3);
-    enable=1;addr0=1;addr1=0; #1000 
-    $display("%b  %b  %b |  %b  %b  %b  %b | O1 Only", enable, addr0, addr1, out0, out1, out2, out3);
-    enable=1;addr0=0;addr1=1; #1000 
-    $display("%b  %b  %b |  %b  %b  %b  %b | O2 Only", enable, addr0, addr1, out0, out1, out2, out3);
-    enable=1;addr0=1;addr1=1; #1000 
-    $display("%b  %b  %b |  %b  %b  %b  %b | O3 Only", enable, addr0, addr1, out0, out1, out2, out3);
-    end
-
-endmodule
+// Decoder testbench
+`timescale 1 ns / 1 ps
+`include "decoder.v"
+
+module testDecoder (); 
+    wire out0,out1,out2,out3;
+	wire Sout0, Sout1, Sout2, Sout3;
+    reg addr0, addr1;
+    reg enable;
+
+
+    behavioralDecoder decoder (out0,out1,out2,out3,addr0,addr1,enable);
+    structuralDecoder structuraltest(Sout0,Sout1,Sout2,Sout3,addr0,addr1,enable); 
+
+    initial begin
+
+	$dumpfile("decoder.vcd");
+	$dumpvars();
+
+	$display("Behavioral Decoder");
+    $display("En A0 A1| O0 O1 O2 O3 | Expected Output");
+    enable=0;addr0=0;addr1=0; #1000 
+    $display("%b  %b  %b |  %b  %b  %b  %b | All false", enable, addr0, addr1, out0, out1, out2, out3);
+    enable=0;addr0=1;addr1=0; #1000
+    $display("%b  %b  %b |  %b  %b  %b  %b | All false", enable, addr0, addr1, out0, out1, out2, out3);
+    enable=0;addr0=0;addr1=1; #1000 
+    $display("%b  %b  %b |  %b  %b  %b  %b | All false", enable, addr0, addr1, out0, out1, out2, out3);
+    enable=0;addr0=1;addr1=1; #1000 
+    $display("%b  %b  %b |  %b  %b  %b  %b | All false", enable, addr0, addr1, out0, out1, out2, out3);
+    enable=1;addr0=0;addr1=0; #1000 
+    $display("%b  %b  %b |  %b  %b  %b  %b | O0 Only", enable, addr0, addr1, out0, out1, out2, out3);
+    enable=1;addr0=1;addr1=0; #1000 
+    $display("%b  %b  %b |  %b  %b  %b  %b | O1 Only", enable, addr0, addr1, out0, out1, out2, out3);
+    enable=1;addr0=0;addr1=1; #1000 
+    $display("%b  %b  %b |  %b  %b  %b  %b | O2 Only", enable, addr0, addr1, out0, out1, out2, out3);
+    enable=1;addr0=1;addr1=1; #1000 
+    $display("%b  %b  %b |  %b  %b  %b  %b | O3 Only", enable, addr0, addr1, out0, out1, out2, out3);
+
+	$display("Structural Decoder");
+    $display("En A0 A1| O0 O1 O2 O3 | Expected Output");
+    enable=0;addr0=0;addr1=0; #1000 
+    $display("%b  %b  %b |  %b  %b  %b  %b | All false", enable, addr0, addr1, Sout0, Sout1, Sout2, Sout3);
+    enable=0;addr0=1;addr1=0; #1000
+    $display("%b  %b  %b |  %b  %b  %b  %b | All false", enable, addr0, addr1, Sout0, Sout1, Sout2, Sout3);
+    enable=0;addr0=0;addr1=1; #1000 
+    $display("%b  %b  %b |  %b  %b  %b  %b | All false", enable, addr0, addr1, Sout0, Sout1, Sout2, Sout3);
+    enable=0;addr0=1;addr1=1; #1000 
+    $display("%b  %b  %b |  %b  %b  %b  %b | All false", enable, addr0, addr1, Sout0, Sout1, Sout2, Sout3);
+    enable=1;addr0=0;addr1=0; #1000 
+    $display("%b  %b  %b |  %b  %b  %b  %b | O0 Only", enable, addr0, addr1, Sout0, Sout1, Sout2, Sout3);
+    enable=1;addr0=1;addr1=0; #1000 
+    $display("%b  %b  %b |  %b  %b  %b  %b | O1 Only", enable, addr0, addr1, Sout0, Sout1, Sout2, Sout3);
+    enable=1;addr0=0;addr1=1; #1000 
+    $display("%b  %b  %b |  %b  %b  %b  %b | O2 Only", enable, addr0, addr1, Sout0, Sout1, Sout2, Sout3);
+    enable=1;addr0=1;addr1=1; #1000 
+    $display("%b  %b  %b |  %b  %b  %b  %b | O3 Only", enable, addr0, addr1, Sout0, Sout1, Sout2, Sout3);
+    end
+endmodule
diff --git a/decoder.v b/decoder.v
index 17836e0..17676fc 100644
--- a/decoder.v
+++ b/decoder.v
@@ -1,22 +1,46 @@
-// Decoder circuit
-
-module behavioralDecoder
-(
-    output out0, out1, out2, out3,
-    input address0, address1,
-    input enable
-);
-    // Uses concatenation and shift operators
-    assign {out3,out2,out1,out0}=enable<<{address1,address0};
-endmodule
-
-
-module structuralDecoder
-(
-    output out0, out1, out2, out3,
-    input address0, address1,
-    input enable
-);
-    // Your decoder code here
-endmodule
-
+// Decoder circuit
+`define AND and #50
+`define OR or #50
+`define NOT not #50
+`define XOR xor #50
+
+module behavioralDecoder
+(
+    output out0, out1, out2, out3,
+    input address0, address1,
+    input enable
+);
+    // Uses concatenation and shift operators
+    assign {out3,out2,out1,out0}=enable<<{address1,address0};
+endmodule
+
+
+module structuralDecoder
+(
+    output Sout0, Sout1, Sout2, Sout3,
+    input address0, address1,
+    input enable
+);
+    // Your decoder code here
+	wire naddress0;
+	wire naddress1;
+	wire nA0nA1;
+	wire A0nA1;
+	wire nA0A1;
+	wire A0A1;
+
+	`NOT A0inv(naddress0, address0);
+	`NOT A1inv(naddress1, address1);
+	`AND andgate1(nA0nA1, naddress0, naddress1);
+	`AND andgate2(Sout0, enable, nA0nA1);
+
+	`AND andgate3(A0nA1, address0, naddress1);
+	`AND andgate4(Sout1, enable, A0nA1);
+
+	`AND andgate5(nA0A1, naddress0, address1);
+	`AND andgate6(Sout2, enable, nA0A1);
+
+	`AND andgate7(A0A1, address0, address1);
+	`AND andgate8(Sout3, enable, A0A1);
+
+endmodule
diff --git a/decoder.vcd b/decoder.vcd
new file mode 100644
index 0000000..2f38a2a
--- /dev/null
+++ b/decoder.vcd
@@ -0,0 +1,272 @@
+$date
+	Thu Sep 21 19:55:29 2017
+$end
+$version
+	Icarus Verilog
+$end
+$timescale
+	1ps
+$end
+$scope module testDecoder $end
+$var wire 1 ! Sout0 $end
+$var wire 1 " Sout1 $end
+$var wire 1 # Sout2 $end
+$var wire 1 $ Sout3 $end
+$var wire 1 % out0 $end
+$var wire 1 & out1 $end
+$var wire 1 ' out2 $end
+$var wire 1 ( out3 $end
+$var reg 1 ) addr0 $end
+$var reg 1 * addr1 $end
+$var reg 1 + enable $end
+$scope module decoder $end
+$var wire 1 , address0 $end
+$var wire 1 - address1 $end
+$var wire 1 . enable $end
+$var wire 1 % out0 $end
+$var wire 1 & out1 $end
+$var wire 1 ' out2 $end
+$var wire 1 ( out3 $end
+$upscope $end
+$scope module structuraltest $end
+$var wire 1 / A0A1 $end
+$var wire 1 0 A0nA1 $end
+$var wire 1 ! Sout0 $end
+$var wire 1 " Sout1 $end
+$var wire 1 # Sout2 $end
+$var wire 1 $ Sout3 $end
+$var wire 1 , address0 $end
+$var wire 1 - address1 $end
+$var wire 1 . enable $end
+$var wire 1 1 nA0A1 $end
+$var wire 1 2 nA0nA1 $end
+$var wire 1 3 naddress0 $end
+$var wire 1 4 naddress1 $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+#0
+$dumpvars
+z4
+z3
+x2
+z1
+z0
+z/
+0.
+0-
+0,
+0+
+0*
+0)
+0(
+0'
+0&
+0%
+z$
+z#
+z"
+z!
+$end
+#50000
+0$
+0/
+0#
+01
+0"
+00
+0!
+13
+14
+#100000
+12
+#1000000
+1)
+1,
+#1050000
+03
+10
+#1100000
+02
+#2000000
+1*
+1-
+0)
+0,
+#2050000
+04
+13
+00
+#2100000
+11
+#3000000
+1)
+1,
+#3050000
+03
+1/
+#3100000
+01
+#4000000
+1%
+0*
+0-
+0)
+0,
+1+
+1.
+#4050000
+14
+13
+0/
+1$
+#4100000
+12
+0$
+#4150000
+1!
+#5000000
+0%
+1&
+1)
+1,
+#5050000
+03
+10
+#5100000
+02
+1"
+#5150000
+0!
+#6000000
+1'
+0&
+1*
+1-
+0)
+0,
+#6050000
+04
+13
+00
+#6100000
+11
+0"
+#6150000
+1#
+#7000000
+0'
+1(
+1)
+1,
+#7050000
+03
+1/
+#7100000
+01
+1$
+#7150000
+0#
+#8000000
+0(
+0*
+0-
+0)
+0,
+0+
+0.
+#8050000
+14
+13
+0/
+0$
+#8100000
+12
+#9000000
+1)
+1,
+#9050000
+03
+10
+#9100000
+02
+#10000000
+1*
+1-
+0)
+0,
+#10050000
+04
+13
+00
+#10100000
+11
+#11000000
+1)
+1,
+#11050000
+03
+1/
+#11100000
+01
+#12000000
+1%
+0*
+0-
+0)
+0,
+1+
+1.
+#12050000
+14
+13
+0/
+1$
+#12100000
+12
+0$
+#12150000
+1!
+#13000000
+0%
+1&
+1)
+1,
+#13050000
+03
+10
+#13100000
+02
+1"
+#13150000
+0!
+#14000000
+1'
+0&
+1*
+1-
+0)
+0,
+#14050000
+04
+13
+00
+#14100000
+11
+0"
+#14150000
+1#
+#15000000
+0'
+1(
+1)
+1,
+#15050000
+03
+1/
+#15100000
+01
+1$
+#15150000
+0#
+#16000000
diff --git a/multiplexer b/multiplexer
new file mode 100755
index 0000000..3bb09b3
--- /dev/null
+++ b/multiplexer
@@ -0,0 +1,155 @@
+#! /usr/bin/vvp
+:ivl_version "0.9.7 " "(v0_9_7)";
+:vpi_time_precision - 12;
+:vpi_module "system";
+:vpi_module "v2005_math";
+:vpi_module "va_math";
+S_0x21d0510 .scope module, "testMultiplexer" "testMultiplexer" 2 5;
+ .timescale -9 -12;
+v0x21fe3a0_0 .net "address", 1 0, L_0x21fead0; 1 drivers
+v0x21fe420_0 .var "address0", 0 0;
+v0x21fe4f0_0 .var "address1", 0 0;
+v0x21fe5c0_0 .var "in0", 0 0;
+v0x21fe690_0 .var "in1", 0 0;
+v0x21fe760_0 .var "in2", 0 0;
+v0x21fe830_0 .var "in3", 0 0;
+v0x21fe900_0 .net "inputs", 3 0, L_0x21feb70; 1 drivers
+v0x21fe9d0_0 .net "out", 0 0, L_0x21ff110; 1 drivers
+v0x21fea50_0 .net "structuralOut", 0 0, L_0x21ffa50; 1 drivers
+L_0x21fead0 .concat [ 1 1 0 0], v0x21fe420_0, v0x21fe4f0_0;
+L_0x21feb70 .concat [ 1 1 1 1], v0x21fe5c0_0, v0x21fe690_0, v0x21fe760_0, v0x21fe830_0;
+S_0x21fdd00 .scope module, "multiplexer" "behavioralMultiplexer" 2 14, 3 6, S_0x21d0510;
+ .timescale -9 -12;
+v0x21fddf0_0 .net "address", 1 0, L_0x21fef20; 1 drivers
+v0x21fdeb0_0 .net "address0", 0 0, v0x21fe420_0; 1 drivers
+v0x21fdf30_0 .net "address1", 0 0, v0x21fe4f0_0; 1 drivers
+v0x21fdfe0_0 .net "in0", 0 0, v0x21fe5c0_0; 1 drivers
+v0x21fe0c0_0 .net "in1", 0 0, v0x21fe690_0; 1 drivers
+v0x21fe170_0 .net "in2", 0 0, v0x21fe760_0; 1 drivers
+v0x21fe1f0_0 .net "in3", 0 0, v0x21fe830_0; 1 drivers
+v0x21fe2a0_0 .net "inputs", 3 0, L_0x21fec10; 1 drivers
+v0x21fe320_0 .alias "out", 0 0, v0x21fe9d0_0;
+L_0x21fec10 .concat [ 1 1 1 1], v0x21fe5c0_0, v0x21fe690_0, v0x21fe760_0, v0x21fe830_0;
+L_0x21fef20 .concat [ 1 1 0 0], v0x21fe420_0, v0x21fe4f0_0;
+L_0x21ff110 .part/v L_0x21fec10, L_0x21fef20, 1;
+S_0x21b6950 .scope module, "structural" "structuralMultiplexer" 2 27, 3 19, S_0x21d0510;
+ .timescale -9 -12;
+L_0x21ff1b0/d .functor NOT 1, v0x21fe420_0, C4<0>, C4<0>, C4<0>;
+L_0x21ff1b0 .delay (50000,50000,50000) L_0x21ff1b0/d;
+L_0x21ff210/d .functor AND 1, v0x21fe5c0_0, L_0x21ff1b0, C4<1>, C4<1>;
+L_0x21ff210 .delay (50000,50000,50000) L_0x21ff210/d;
+L_0x21ff2b0/d .functor NOT 1, v0x21fe4f0_0, C4<0>, C4<0>, C4<0>;
+L_0x21ff2b0 .delay (50000,50000,50000) L_0x21ff2b0/d;
+L_0x21ff350/d .functor AND 1, L_0x21ff2b0, L_0x21ff210, C4<1>, C4<1>;
+L_0x21ff350 .delay (50000,50000,50000) L_0x21ff350/d;
+L_0x21ff3f0/d .functor AND 1, v0x21fe690_0, v0x21fe420_0, C4<1>, C4<1>;
+L_0x21ff3f0 .delay (50000,50000,50000) L_0x21ff3f0/d;
+L_0x21ff490/d .functor AND 1, L_0x21ff3f0, L_0x21ff2b0, C4<1>, C4<1>;
+L_0x21ff490 .delay (50000,50000,50000) L_0x21ff490/d;
+L_0x21ff610/d .functor AND 1, v0x21fe760_0, L_0x21ff1b0, C4<1>, C4<1>;
+L_0x21ff610 .delay (50000,50000,50000) L_0x21ff610/d;
+L_0x21ff6d0/d .functor AND 1, L_0x21ff610, v0x21fe4f0_0, C4<1>, C4<1>;
+L_0x21ff6d0 .delay (50000,50000,50000) L_0x21ff6d0/d;
+L_0x21ff7e0/d .functor AND 1, v0x21fe830_0, v0x21fe420_0, C4<1>, C4<1>;
+L_0x21ff7e0 .delay (50000,50000,50000) L_0x21ff7e0/d;
+L_0x21ff8b0/d .functor AND 1, L_0x21ff7e0, v0x21fe4f0_0, C4<1>, C4<1>;
+L_0x21ff8b0 .delay (50000,50000,50000) L_0x21ff8b0/d;
+L_0x21ffa50/d .functor OR 1, L_0x21ff350, L_0x21ff490, L_0x21ff6d0, L_0x21ff8b0;
+L_0x21ffa50 .delay (50000,50000,50000) L_0x21ffa50/d;
+v0x21d8670_0 .net "I0A0", 0 0, L_0x21ff210; 1 drivers
+v0x21fd100_0 .net "I0A1", 0 0, L_0x21ff350; 1 drivers
+v0x21fd1a0_0 .net "I1A0", 0 0, L_0x21ff3f0; 1 drivers
+v0x21fd240_0 .net "I1A1", 0 0, L_0x21ff490; 1 drivers
+v0x21fd2f0_0 .net "I2A0", 0 0, L_0x21ff610; 1 drivers
+v0x21fd390_0 .net "I2A1", 0 0, L_0x21ff6d0; 1 drivers
+v0x21fd470_0 .net "I3A0", 0 0, L_0x21ff7e0; 1 drivers
+v0x21fd510_0 .net "I3A1", 0 0, L_0x21ff8b0; 1 drivers
+v0x21fd600_0 .alias "address0", 0 0, v0x21fdeb0_0;
+v0x21fd6a0_0 .alias "address1", 0 0, v0x21fdf30_0;
+v0x21fd7a0_0 .alias "in0", 0 0, v0x21fdfe0_0;
+v0x21fd840_0 .alias "in1", 0 0, v0x21fe0c0_0;
+v0x21fd950_0 .alias "in2", 0 0, v0x21fe170_0;
+v0x21fd9f0_0 .alias "in3", 0 0, v0x21fe1f0_0;
+v0x21fdb10_0 .net "naddress0", 0 0, L_0x21ff1b0; 1 drivers
+v0x21fdbb0_0 .net "naddress1", 0 0, L_0x21ff2b0; 1 drivers
+v0x21fda70_0 .alias "structuralOut", 0 0, v0x21fea50_0;
+    .scope S_0x21d0510;
+T_0 ;
+    %vpi_call 2 31 "$dumpfile", "multiplexer.vcd";
+    %vpi_call 2 32 "$dumpvars";
+    %vpi_call 2 34 "$display", "Behavioral Multiplexer";
+    %vpi_call 2 35 "$display", "A0 A1| I3 I2 I1 I0 | Output | Expected Output";
+    %set/v v0x21fe420_0, 0, 1;
+    %set/v v0x21fe4f0_0, 0, 1;
+    %set/v v0x21fe5c0_0, 1, 1;
+    %set/v v0x21fe690_0, 0, 1;
+    %set/v v0x21fe760_0, 0, 1;
+    %set/v v0x21fe830_0, 0, 1;
+    %delay 1000000, 0;
+    %vpi_call 2 37 "$display", "%b  %b |  %b  %b  %b  %b | %b | I0", v0x21fe4f0_0, v0x21fe420_0, v0x21fe830_0, v0x21fe760_0, v0x21fe690_0, v0x21fe5c0_0, v0x21fe9d0_0;
+    %set/v v0x21fe420_0, 1, 1;
+    %set/v v0x21fe4f0_0, 0, 1;
+    %set/v v0x21fe5c0_0, 0, 1;
+    %set/v v0x21fe690_0, 1, 1;
+    %set/v v0x21fe760_0, 0, 1;
+    %set/v v0x21fe830_0, 0, 1;
+    %delay 1000000, 0;
+    %vpi_call 2 39 "$display", "%b  %b |  %b  %b  %b  %b | %b | I1", v0x21fe4f0_0, v0x21fe420_0, v0x21fe830_0, v0x21fe760_0, v0x21fe690_0, v0x21fe5c0_0, v0x21fe9d0_0;
+    %set/v v0x21fe420_0, 0, 1;
+    %set/v v0x21fe4f0_0, 1, 1;
+    %set/v v0x21fe5c0_0, 0, 1;
+    %set/v v0x21fe690_0, 0, 1;
+    %set/v v0x21fe760_0, 1, 1;
+    %set/v v0x21fe830_0, 0, 1;
+    %delay 1000000, 0;
+    %vpi_call 2 41 "$display", "%b  %b |  %b  %b  %b  %b | %b | I2", v0x21fe4f0_0, v0x21fe420_0, v0x21fe830_0, v0x21fe760_0, v0x21fe690_0, v0x21fe5c0_0, v0x21fe9d0_0;
+    %set/v v0x21fe420_0, 1, 1;
+    %set/v v0x21fe4f0_0, 1, 1;
+    %set/v v0x21fe5c0_0, 0, 1;
+    %set/v v0x21fe690_0, 0, 1;
+    %set/v v0x21fe760_0, 0, 1;
+    %set/v v0x21fe830_0, 1, 1;
+    %delay 1000000, 0;
+    %vpi_call 2 43 "$display", "%b  %b |  %b  %b  %b  %b | %b | I3", v0x21fe4f0_0, v0x21fe420_0, v0x21fe830_0, v0x21fe760_0, v0x21fe690_0, v0x21fe5c0_0, v0x21fe9d0_0;
+    %vpi_call 2 45 "$display", "Structural Multiplexer";
+    %vpi_call 2 46 "$display", "A0 A1| I3 I2 I1 I0 | Output | Expected Output";
+    %set/v v0x21fe420_0, 0, 1;
+    %set/v v0x21fe4f0_0, 0, 1;
+    %set/v v0x21fe5c0_0, 1, 1;
+    %set/v v0x21fe690_0, 0, 1;
+    %set/v v0x21fe760_0, 0, 1;
+    %set/v v0x21fe830_0, 0, 1;
+    %delay 1000000, 0;
+    %vpi_call 2 48 "$display", "%b  %b |  %b  %b  %b  %b | %b | I0", v0x21fe4f0_0, v0x21fe420_0, v0x21fe830_0, v0x21fe760_0, v0x21fe690_0, v0x21fe5c0_0, v0x21fea50_0;
+    %set/v v0x21fe420_0, 1, 1;
+    %set/v v0x21fe4f0_0, 0, 1;
+    %set/v v0x21fe5c0_0, 0, 1;
+    %set/v v0x21fe690_0, 1, 1;
+    %set/v v0x21fe760_0, 0, 1;
+    %set/v v0x21fe830_0, 0, 1;
+    %delay 1000000, 0;
+    %vpi_call 2 53 "$display", "%b  %b |  %b  %b  %b  %b | %b | I1", v0x21fe4f0_0, v0x21fe420_0, v0x21fe830_0, v0x21fe760_0, v0x21fe690_0, v0x21fe5c0_0, v0x21fea50_0;
+    %set/v v0x21fe420_0, 0, 1;
+    %set/v v0x21fe4f0_0, 1, 1;
+    %set/v v0x21fe5c0_0, 0, 1;
+    %set/v v0x21fe690_0, 0, 1;
+    %set/v v0x21fe760_0, 1, 1;
+    %set/v v0x21fe830_0, 0, 1;
+    %delay 1000000, 0;
+    %vpi_call 2 58 "$display", "%b  %b |  %b  %b  %b  %b | %b | I2", v0x21fe4f0_0, v0x21fe420_0, v0x21fe830_0, v0x21fe760_0, v0x21fe690_0, v0x21fe5c0_0, v0x21fea50_0;
+    %set/v v0x21fe420_0, 1, 1;
+    %set/v v0x21fe4f0_0, 1, 1;
+    %set/v v0x21fe5c0_0, 0, 1;
+    %set/v v0x21fe690_0, 0, 1;
+    %set/v v0x21fe760_0, 0, 1;
+    %set/v v0x21fe830_0, 1, 1;
+    %delay 1000000, 0;
+    %vpi_call 2 63 "$display", "%b  %b |  %b  %b  %b  %b | %b | I3", v0x21fe4f0_0, v0x21fe420_0, v0x21fe830_0, v0x21fe760_0, v0x21fe690_0, v0x21fe5c0_0, v0x21fea50_0;
+    %end;
+    .thread T_0;
+# The file index is used to find the file name in the following table.
+:file_names 4;
+    "N/A";
+    "<interactive>";
+    "multiplexer.t.v";
+    "./multiplexer.v";
diff --git a/multiplexer.t.v b/multiplexer.t.v
index fd475c4..3aab091 100644
--- a/multiplexer.t.v
+++ b/multiplexer.t.v
@@ -1,7 +1,68 @@
-// Multiplexer testbench
-`timescale 1 ns / 1 ps
-`include "multiplexer.v"
-
-module testMultiplexer ();
-  // Your test code here
-endmodule
+// Multiplexer testbench
+`timescale 1 ns / 1 ps
+`include "multiplexer.v"
+
+module testMultiplexer ();
+  // Your test code here
+
+	reg in0, in1, in2, in3;
+	reg address0, address1;
+	wire out;
+	wire[1:0] address = {address1, address0};
+    	wire[3:0] inputs = {in3, in2, in1, in0};
+
+	behavioralMultiplexer multiplexer(out, address0, address1, in0, in1, in2, in3);
+	
+	wire naddress0;
+	wire I0A0;
+	wire naddress1;
+	wire I0A1;
+	wire I1A0;
+	wire I1A1;
+	wire I2A0;
+	wire I2A1;
+	wire I3A0;
+	wire I3A1;
+
+	structuralMultiplexer structural(address0, address1, in0, in1, in2, in3, structuralOut);
+		
+    initial begin
+
+	$dumpfile("multiplexer.vcd");
+	$dumpvars();
+
+	$display("Behavioral Multiplexer");
+    $display("A0 A1| I3 I2 I1 I0 | Output | Expected Output");
+    address0=0; address1 = 0; in0=1; in1 = 0; in2 = 0; in3 = 0; #1000 
+    $display("%b  %b |  %b  %b  %b  %b | %b | I0", address1, address0, in3, in2, in1, in0, out);
+    address0=1; address1 = 0; in0=0; in1 = 1; in2 = 0; in3 = 0; #1000 
+    $display("%b  %b |  %b  %b  %b  %b | %b | I1", address1, address0, in3, in2, in1, in0, out);
+    address0=0; address1 = 1; in0=0; in1 = 0; in2 = 1; in3 = 0; #1000 
+    $display("%b  %b |  %b  %b  %b  %b | %b | I2", address1, address0, in3, in2, in1, in0, out);
+    address0=1; address1 = 1; in0=0; in1 = 0; in2 = 0; in3 = 1; #1000 
+    $display("%b  %b |  %b  %b  %b  %b | %b | I3", address1, address0, in3, in2, in1, in0, out);
+
+	$display("Structural Multiplexer");
+    $display("A0 A1| I3 I2 I1 I0 | Output | Expected Output");
+    address0=0; address1 = 0; in0=1; in1 = 0; in2 = 0; in3 = 0; #1000 
+    $display("%b  %b |  %b  %b  %b  %b | %b | I0", address1, address0, in3, in2, in1, in0, structuralOut);
+    //address0=0; address1 = 0; in0=1'bX; in1 = 0; in2 = 0; in3 = 0; #1000 
+    //$display("%b  %b |  %b  %b  %b  %b | %b | I0", address1, address0, in3, in2, in1, in0, structuralOut);
+
+    address0=1; address1 = 0; in0=0; in1 = 1; in2 = 0; in3 = 0; #1000 
+	$display("%b  %b |  %b  %b  %b  %b | %b | I1", address1, address0, in3, in2, in1, in0, structuralOut);
+    //address0=1; address1 = 0; in0=0; in1 = 1'bX; in2 = 0; in3 = 0; #1000 
+    //$display("%b  %b |  %b  %b  %b  %b | %b | I1", address1, address0, in3, in2, in1, in0, structuralOut);
+    
+	address0=0; address1 = 1; in0=0; in1 = 0; in2 = 1; in3 = 0; #1000 
+	$display("%b  %b |  %b  %b  %b  %b | %b | I2", address1, address0, in3, in2, in1, in0, structuralOut);
+    //address0=0; address1 = 1; in0=0; in1 = 0; in2 = 1'bX; in3 = 0; #1000 
+    //$display("%b  %b |  %b  %b  %b  %b | %b | I2", address1, address0, in3, in2, in1, in0, structuralOut);
+
+    address0=1; address1 = 1; in0=0; in1 = 0; in2 = 0; in3 = 1; #1000 
+	$display("%b  %b |  %b  %b  %b  %b | %b | I3", address1, address0, in3, in2, in1, in0, structuralOut);
+    //address0=1; address1 = 1; in0=0; in1 = 0; in2 = 0; in3 = 1'bX; #1000 
+    //$display("%b  %b |  %b  %b  %b  %b | %b | I3", address1, address0, in3, in2, in1, in0, structuralOut);
+	end
+
+endmodule
diff --git a/multiplexer.v b/multiplexer.v
index b05820f..e3752fb 100644
--- a/multiplexer.v
+++ b/multiplexer.v
@@ -1,24 +1,63 @@
-// Multiplexer circuit
-
-module behavioralMultiplexer
-(
-    output out,
-    input address0, address1,
-    input in0, in1, in2, in3
-);
-    // Join single-bit inputs into a bus, use address as index
-    wire[3:0] inputs = {in3, in2, in1, in0};
-    wire[1:0] address = {address1, address0};
-    assign out = inputs[address];
-endmodule
-
-
-module structuralMultiplexer
-(
-    output out,
-    input address0, address1,
-    input in0, in1, in2, in3
-);
-    // Your multiplexer code here
-endmodule
-
+// Multiplexer circuit
+`define AND and #50
+`define OR or #50
+`define NOT not #50
+
+module behavioralMultiplexer
+(
+    output out,
+    input address0, address1,
+    input in0, in1, in2, in3
+);
+    // Join single-bit inputs into a bus, use address as index
+    wire[3:0] inputs = {in3, in2, in1, in0};
+    wire[1:0] address = {address1, address0};
+    assign out = inputs[address];
+endmodule
+
+
+module structuralMultiplexer
+(
+    input address0, address1,
+    input in0, in1, in2, in3,
+    output structuralOut 
+);
+	wire naddress0;
+	wire I0A0;
+	wire naddress1;
+
+	wire I1A0;
+	wire I1A1;
+	
+	wire I2A0;
+	wire I2A1;
+
+	wire I3A0;
+	wire I3A1;
+
+
+//Go through all four inputs
+
+//Input 0 is (I0 & ~S0) & ((I0 & ~S0) & ~S1)
+	`NOT A0inv(naddress0, address0);
+	`AND andgate1(I0A0, in0, naddress0);
+	`NOT A1inv(naddress1, address1);
+	`AND andgate2(I0A1, naddress1, I0A0);
+	
+//Input 1 is (I1 & S0) & ((I1 & S0) & ~S1)
+    	`AND andgate3(I1A0, in1, address0);
+	`AND andgate4(I1A1, I1A0, naddress1);
+
+//Input 2 is (I2 & ~S0) & ((I2 & ~S0) & S1)
+	`AND andgate5(I2A0, in2, naddress0);
+	`AND andgate6(I2A1, I2A0, address1);
+
+//Input 3 is (I3 & S0) & ((I3 & S0) & S1)
+	`AND andgate7(I3A0, in3, address0);
+	`AND andgate8(I3A1, I3A0, address1);
+
+//Final Or Gate
+
+	`OR orgate(structuralOut, I0A1, I1A1, I2A1, I3A1);
+
+endmodule
diff --git a/multiplexer.vcd b/multiplexer.vcd
new file mode 100644
index 0000000..bd66e1d
--- /dev/null
+++ b/multiplexer.vcd
@@ -0,0 +1,254 @@
+$date
+	Thu Sep 21 20:14:10 2017
+$end
+$version
+	Icarus Verilog
+$end
+$timescale
+	1ps
+$end
+$scope module testMultiplexer $end
+$var wire 2 ! address [1:0] $end
+$var wire 4 " inputs [3:0] $end
+$var wire 1 # out $end
+$var wire 1 $ structuralOut $end
+$var reg 1 % address0 $end
+$var reg 1 & address1 $end
+$var reg 1 ' in0 $end
+$var reg 1 ( in1 $end
+$var reg 1 ) in2 $end
+$var reg 1 * in3 $end
+$scope module multiplexer $end
+$var wire 2 + address [1:0] $end
+$var wire 1 , address0 $end
+$var wire 1 - address1 $end
+$var wire 1 . in0 $end
+$var wire 1 / in1 $end
+$var wire 1 0 in2 $end
+$var wire 1 1 in3 $end
+$var wire 4 2 inputs [3:0] $end
+$var wire 1 # out $end
+$upscope $end
+$scope module structural $end
+$var wire 1 3 I0A0 $end
+$var wire 1 4 I0A1 $end
+$var wire 1 5 I1A0 $end
+$var wire 1 6 I1A1 $end
+$var wire 1 7 I2A0 $end
+$var wire 1 8 I2A1 $end
+$var wire 1 9 I3A0 $end
+$var wire 1 : I3A1 $end
+$var wire 1 , address0 $end
+$var wire 1 - address1 $end
+$var wire 1 . in0 $end
+$var wire 1 / in1 $end
+$var wire 1 0 in2 $end
+$var wire 1 1 in3 $end
+$var wire 1 ; naddress0 $end
+$var wire 1 < naddress1 $end
+$var wire 1 $ structuralOut $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+#0
+$dumpvars
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