diff --git a/Writeup.md b/Writeup.md
new file mode 100644
index 0000000..816e3d0
--- /dev/null
+++ b/Writeup.md
@@ -0,0 +1,8 @@
+# Writeup HW 4
+## Deliverable 1
+![diagrams](https://github.com/TShapinsky/HW4/blob/master/diagrams.jpg?raw=true)
+## Deliverable 6
+```verilog
+    assign out = enable<<address; 
+```
+Acts as a decoder because the bitshift operator is defined as shifting all the bits of a number over by n bits. In this case we are shifting `enable`, this means that if enable is low the output will always be 0 (this is the expected value) and if it is high the output will be a 1 in the bit equal to the input address. 
diff --git a/diagrams.jpg b/diagrams.jpg
new file mode 100644
index 0000000..d2f0e33
Binary files /dev/null and b/diagrams.jpg differ
diff --git a/mux.v b/mux.v
new file mode 100644
index 0000000..58d0b59
--- /dev/null
+++ b/mux.v
@@ -0,0 +1,54 @@
+module mux32to1by1
+  (
+   output 	out,
+   input [4:0] 	address,
+   input [31:0] inputs
+   );
+   assign out = inputs[address];
+   
+endmodule
+
+module mux32to1by32
+  (
+   output [31:0] out,
+   input [4:0] 	 address,
+   input [31:0]  input0, input1, input2, input3, input4, input5, input6, input7, input8, input9, input10, input11, input12, input13, input14, input15, input16, input17, input18, input19, input20, input21, input22, input23, input24, input25, input26, input27, input28, input29, input30, input31
+   );
+   
+   wire [31:0] 	 mux[31:0];			// Create a 2D array of wires
+   assign mux[0] = input0;		// Connect the sources of the array
+   assign mux[1] = input1;
+   assign mux[2] = input2;
+   assign mux[3] = input3;
+   assign mux[4] = input4;
+   assign mux[5] = input5;
+   assign mux[6] = input6;
+   assign mux[7] = input7;
+   assign mux[8] = input8;
+   assign mux[9] = input9;
+   assign mux[10] = input10;
+   assign mux[11] = input11;
+   assign mux[12] = input12;
+   assign mux[13] = input13;
+   assign mux[14] = input14;
+   assign mux[15] = input15;
+   assign mux[16] = input16;
+   assign mux[17] = input17;
+   assign mux[18] = input18;
+   assign mux[19] = input19;
+   assign mux[20] = input20;
+   assign mux[21] = input21;
+   assign mux[22] = input22;
+   assign mux[23] = input23;
+   assign mux[24] = input24;
+   assign mux[25] = input25;
+   assign mux[26] = input26;
+   assign mux[27] = input27;
+   assign mux[28] = input28;
+   assign mux[29] = input29;
+   assign mux[30] = input30;
+   assign mux[31] = input31;
+   assign out = mux[address];	// Connect the output of the array
+   //assign out = inputs[address];
+   
+endmodule
diff --git a/regfile.t.v b/regfile.t.v
index f13815a..fdf9962 100644
--- a/regfile.t.v
+++ b/regfile.t.v
@@ -1,3 +1,4 @@
+`include "regfile.v"
 //------------------------------------------------------------------------------
 // Test harness validates hw4testbench by connecting it to various functional 
 // or broken register files, and verifying that it correctly identifies each
@@ -138,6 +139,77 @@ output reg		Clk
     $display("Test Case 2 Failed");
   end
 
+  // Test Case 3:
+  // Write 10 to register 2, Write '5' to register 2 with write enable low, verify value is still 10
+     WriteRegister = 5'd2;
+     WriteData = 32'd10;
+     RegWrite = 1;
+     #5 Clk=1; #5 Clk=0;
+     ReadRegister1 = 5'd2;
+     RegWrite = 0;
+     WriteData = 32'd5;
+     #5 Clk=1; #5 Clk=0;
+
+     if(ReadData1 != 10) begin
+	dutpassed = 0;
+	$display("Test Case 3 Failed");
+     end
+
+  // Test Case 4:
+  // Write 10 to register 2, Write '5' to register 3, verify value is still 10
+     WriteRegister = 5'd2;
+     WriteData = 32'd10;
+     RegWrite = 1;
+     #5 Clk=1; #5 Clk=0;
+     WriteRegister = 5'd3;
+     ReadRegister1 = 5'd2;
+     WriteData = 32'd5;
+     #5 Clk=1; #5 Clk=0;
+
+     if(ReadData1 != 10) begin
+	dutpassed = 0;
+	$display("Test Case 4 Failed");
+     end
+
+  // Test Case 5:
+  // Write 10 to register 0, verify value is still 0
+     WriteRegister = 5'd0;
+     WriteData = 32'd10;
+     RegWrite = 1;
+     ReadRegister1 = 5'd0;
+     #5 Clk=1; #5 Clk=0;
+
+     if(ReadData1 != 0) begin
+	dutpassed = 0;
+	$display("Test Case 5 Failed");
+     end
+
+  // Test Case 6:
+  // Write 10 to register 2, verify with both reads, Write '5' to register 3, verify with both reads
+     WriteRegister = 5'd2;
+     WriteData = 32'd10;
+     RegWrite = 1;
+     ReadRegister1 = 5'd2;
+     ReadRegister2 = 5'd2;
+     #5 Clk=1; #5 Clk=0;
+     
+     if(ReadData1 != ReadData2) begin
+	dutpassed = 0;
+	$display("Test Case 6 Failed");
+     end
+
+     WriteRegister = 5'd3;
+     ReadRegister1 = 5'd3;
+     ReadRegister2 = 5'd3;
+     RegWrite = 1;
+     WriteData = 32'd5;
+     #5 Clk=1; #5 Clk=0;
+
+     if(ReadData1 != ReadData2) begin
+	dutpassed = 0;
+	$display("Test Case 6 Failed");
+     end
+
 
   // All done!  Wait a moment and signal test completion.
   #5
@@ -145,4 +217,4 @@ output reg		Clk
 
 end
 
-endmodule
\ No newline at end of file
+endmodule
diff --git a/regfile.v b/regfile.v
index b8a3c74..378ba93 100644
--- a/regfile.v
+++ b/regfile.v
@@ -1,3 +1,5 @@
+`include "register.v"
+`include "mux.v"
 //------------------------------------------------------------------------------
 // MIPS register file
 //   width: 32 bits
@@ -17,11 +19,30 @@ input[4:0]	WriteRegister,	// Address of register to write
 input		RegWrite,	// Enable writing of register when High
 input		Clk		// Clock (Positive Edge Triggered)
 );
-
+   wire [31:0] 	d [31:0];
+   
+   genvar 	i;
+   generate
+      register32zero zeroreg(d[0], WriteData, 0, Clk);
+      wire 	[31:0] expaddr;
+      assign expaddr = 1 << WriteRegister;
+      
+      for(i = 1; i < (1<<5); i= i + 1) begin: registers
+	 wire select, wrenable;
+	 wire [4:0] addr ;
+	 assign addr = i;
+	 mux32to1by1 muxselect(select, addr, expaddr);
+	 assign wrenable = select & RegWrite; 
+	 register32 regist(d[i], WriteData, wrenable,Clk);
+      end
+   endgenerate
+   mux32to1by32 read1(ReadData1, ReadRegister1, d[0], d[1], d[2], d[3], d[4], d[5], d[6], d[7], d[8], d[9], d[10], d[11], d[12], d[13], d[14], d[15], d[16], d[17], d[18], d[19], d[20], d[21], d[22], d[23], d[24], d[25], d[26], d[27], d[28], d[29], d[30], d[31]);
+   mux32to1by32 read2(ReadData2, ReadRegister2, d[0], d[1], d[2], d[3], d[4], d[5], d[6], d[7], d[8], d[9], d[10], d[11], d[12], d[13], d[14], d[15], d[16], d[17], d[18], d[19], d[20], d[21], d[22], d[23], d[24], d[25], d[26], d[27], d[28], d[29], d[30], d[31]);
+   
   // These two lines are clearly wrong.  They are included to showcase how the 
   // test harness works. Delete them after you understand the testing process, 
   // and replace them with your actual code.
-  assign ReadData1 = 42;
-  assign ReadData2 = 42;
+  //assign ReadData1 = 42;
+  //assign ReadData2 = 42;
 
-endmodule
\ No newline at end of file
+endmodule
diff --git a/register.v b/register.v
index dc9b8cb..859a675 100644
--- a/register.v
+++ b/register.v
@@ -14,4 +14,34 @@ input		clk
         end
     end
 
-endmodule
\ No newline at end of file
+endmodule
+
+// Variable width D Flip-Flop with enable
+//   Positive edge triggered
+
+module register32 #( parameter W = 32)
+(
+output reg [W-1:0] q,
+input      [W-1:0] d,
+input              wrenable,
+input              clk
+);
+
+    always @(posedge clk) begin
+        if(wrenable) begin
+            q = d;
+        end
+    end
+endmodule
+
+module register32zero #( parameter W = 32)
+(
+ output reg [W-1:0] q,
+ input [W-1:0] 	    d,
+ input 		    wrenable,
+ input 		    clk		    
+ );
+   always@( clk )begin
+      assign q = 1'b0;
+   end
+endmodule