diff --git a/HW4_1_and_6.jpg b/HW4_1_and_6.jpg
new file mode 100644
index 0000000..33f7741
Binary files /dev/null and b/HW4_1_and_6.jpg differ
diff --git a/decoders.v b/decoders.v
index dd467c2..4044dac 100644
--- a/decoders.v
+++ b/decoders.v
@@ -10,5 +10,4 @@ input[4:0]	address
 
     assign out = enable<<address; 
 
-endmodule
-
+endmodule
\ No newline at end of file
diff --git a/multiplexers.v b/multiplexers.v
new file mode 100644
index 0000000..83cdd58
--- /dev/null
+++ b/multiplexers.v
@@ -0,0 +1,61 @@
+// 32:1 multiplexer
+module mux32to1by1
+(
+output out,
+input[4:0] address,
+input[31:0] inputs
+);
+	assign out = inputs[address];
+endmodule
+
+
+// 32-bit width and 32-bit depth multiplexer
+module mux32to1by32
+(
+output[31:0] out,
+input[4:0] address,
+input[31:0]
+
+input0,input1,input2,input3,input4,input5,input6,input7,
+input8,input9,input10,input11,input12,input13,input14,input15,
+input16,input17,input18,input19,input20,input21,input22,input23,
+input24,input25,input26,input27,input28,input29,input30,input31
+);
+
+	wire[31:0] mux[31:0];	//create a 2D array of wires
+	assign mux[0] = input0;	//connect the sources of the array
+	assign mux[1] = input1;
+	assign mux[2] = input2;
+	assign mux[3] = input3;
+	assign mux[4] = input4;
+	assign mux[5] = input5;
+	assign mux[6] = input6;
+	assign mux[7] = input7;
+	assign mux[8] = input8;
+	assign mux[9] = input9;
+	assign mux[10] = input10;
+	assign mux[11] = input11;
+	assign mux[12] = input12;
+	assign mux[13] = input13;
+	assign mux[14] = input14;
+	assign mux[15] = input15;
+	assign mux[16] = input16;
+	assign mux[17] = input17;
+	assign mux[18] = input18;
+	assign mux[19] = input19;
+	assign mux[20] = input20;
+	assign mux[21] = input21;
+	assign mux[22] = input22;
+	assign mux[23] = input23;
+	assign mux[24] = input24;
+	assign mux[25] = input25;
+	assign mux[26] = input26;
+	assign mux[27] = input27;
+	assign mux[28] = input28;
+	assign mux[29] = input29;
+	assign mux[30] = input30;
+	assign mux[31] = input31;
+
+	assign out = mux[address];	//connect the output of the array
+
+	endmodule
diff --git a/regfile.t.v b/regfile.t.v
index f13815a..88b1495 100644
--- a/regfile.t.v
+++ b/regfile.t.v
@@ -2,6 +2,7 @@
 // Test harness validates hw4testbench by connecting it to various functional 
 // or broken register files, and verifying that it correctly identifies each
 //------------------------------------------------------------------------------
+`include "regfile.v"
 
 module hw4testbenchharness();
 
@@ -138,6 +139,77 @@ output reg		Clk
     $display("Test Case 2 Failed");
   end
 
+  // Test Case 3: 
+  //  Write a few values to different registers without setting write enable high
+  //  Testing to see if Write Enable is broken or ignored
+
+  // Test Case 3a
+  WriteRegister = 5'd2;
+  WriteData = 32'd8;
+  RegWrite = 0;
+  ReadRegister1 = 5'd2;
+  ReadRegister2 = 5'd2;
+  #5 Clk=1; #5 Clk=0;
+
+  if((ReadData1 == 8) || (ReadData2 == 8)) begin
+    dutpassed = 0;
+    $display("Test Case 3a Failed");
+  end
+
+  // Test Case 3b
+  WriteRegister = 5'd3;
+  WriteData = 32'd13;
+  RegWrite = 0;
+  ReadRegister1 = 5'd3;
+  ReadRegister2 = 5'd3;
+  #5 Clk=1; #5 Clk=0;
+
+  if((ReadData1 == 13) || (ReadData2 == 13)) begin
+    dutpassed = 0;
+    $display("Test Case 3b Failed");
+  end
+
+
+  // Test Case 4 - verify that Register Zero is constant 0 and not a register
+  // Works by trying to write to it and then reading to see if still holds 0
+  WriteRegister = 5'd0;
+  WriteData = 32'd8;
+  RegWrite = 1;
+  ReadRegister1 = 5'd0;
+  ReadRegister2 = 5'd0;
+  #5 Clk=1; #5 Clk=0;
+
+  if((ReadData1 != 0) || (ReadData2 != 0)) begin
+    dutpassed = 0;
+    $display("Test Case 4 Failed");
+  end
+
+
+  // Test Case 5 - verify that write decoder is functioning properly
+  WriteRegister = 5'd1;
+  WriteData = 32'd8;
+  RegWrite = 1;
+  ReadRegister1 = 5'd1;
+  ReadRegister2 = 5'd1;
+  #5 Clk=1; #5 Clk=0;
+
+  if((ReadData1 != 8) || (ReadData2 != 8)) begin
+    dutpassed = 0;
+    $display("Test Case 5 Failed");
+  end
+  WriteRegister = 5'd2;
+  WriteData = 32'd11;
+  RegWrite = 1;
+  ReadRegister1 = 5'd1;
+  ReadRegister2 = 5'd2;
+  #5 Clk=1; #5 Clk=0;
+
+  if((ReadData1 != 8) || (ReadData2 != 11)) begin
+    dutpassed = 0;
+    $display("Test Case 5 Failed");
+  end
+
+  // Fully Perfect Register File - dutpassed = true
 
   // All done!  Wait a moment and signal test completion.
   #5
diff --git a/regfile.v b/regfile.v
index b8a3c74..a0b717e 100644
--- a/regfile.v
+++ b/regfile.v
@@ -6,6 +6,11 @@
 //   1 synchronous, positive edge triggered write port
 //------------------------------------------------------------------------------
 
+`include "register.v"
+`include "decoders.v"
+`include "multiplexers.v"
+
+
 module regfile
 (
 output[31:0]	ReadData1,	// Contents of first register read
@@ -18,10 +23,102 @@ input		RegWrite,	// Enable writing of register when High
 input		Clk		// Clock (Positive Edge Triggered)
 );
 
-  // These two lines are clearly wrong.  They are included to showcase how the 
-  // test harness works. Delete them after you understand the testing process, 
-  // and replace them with your actual code.
-  assign ReadData1 = 42;
-  assign ReadData2 = 42;
+	//prepare to create decoder
+	wire [31:0] dec_out;
+
+	//prepare to create 32 registers, each 32-bit depth
+	wire [31:0] reg0;
+	wire [31:0] reg1;
+	wire [31:0] reg2;
+	wire [31:0] reg3;
+	wire [31:0] reg4;
+	wire [31:0] reg5;
+	wire [31:0] reg6;
+	wire [31:0] reg7;
+	wire [31:0] reg8;
+	wire [31:0] reg9;
+	wire [31:0] reg10;
+	wire [31:0] reg11;
+	wire [31:0] reg12;
+	wire [31:0] reg13;
+	wire [31:0] reg14;
+	wire [31:0] reg15;
+	wire [31:0] reg16;
+	wire [31:0] reg17;
+	wire [31:0] reg18;
+	wire [31:0] reg19;
+	wire [31:0] reg20;
+	wire [31:0] reg21;
+	wire [31:0] reg22;
+	wire [31:0] reg23;
+	wire [31:0] reg24;
+	wire [31:0] reg25;
+	wire [31:0] reg26;
+	wire [31:0] reg27;
+	wire [31:0] reg28;
+	wire [31:0] reg29;
+	wire [31:0] reg30;
+	wire [31:0] reg31;
+
+	//create decoder for handling register writing
+	decoder1to32 decoder(dec_out, RegWrite, WriteRegister); //out, enable, address
+
+	//create registers themselves
+	register32zero reg_0 (reg0, WriteData, dec_out[0], Clk); //zero register takes sets output to zero always.
+	register32 reg_1 (reg1, WriteData, dec_out[1], Clk);
+	register32 reg_2 (reg2, WriteData, dec_out[2], Clk);
+	register32 reg_3 (reg3, WriteData, dec_out[3], Clk);
+	register32 reg_4 (reg4, WriteData, dec_out[4], Clk);
+	register32 reg_5 (reg5, WriteData, dec_out[5], Clk);
+	register32 reg_6 (reg6, WriteData, dec_out[6], Clk);
+	register32 reg_7 (reg7, WriteData, dec_out[7], Clk);
+	register32 reg_8 (reg8, WriteData, dec_out[8], Clk);
+	register32 reg_9 (reg9, WriteData, dec_out[9], Clk);
+	register32 reg_10 (reg10, WriteData, dec_out[10], Clk);
+	register32 reg_11 (reg11, WriteData, dec_out[11], Clk);
+	register32 reg_12 (reg12, WriteData, dec_out[12], Clk);
+	register32 reg_13 (reg13, WriteData, dec_out[13], Clk);
+	register32 reg_14 (reg14, WriteData, dec_out[14], Clk);
+	register32 reg_15 (reg15, WriteData, dec_out[15], Clk);
+	register32 reg_16 (reg16, WriteData, dec_out[16], Clk);
+	register32 reg_17 (reg17, WriteData, dec_out[17], Clk);
+	register32 reg_18 (reg18, WriteData, dec_out[18], Clk);
+	register32 reg_19 (reg19, WriteData, dec_out[19], Clk);
+	register32 reg_20 (reg20, WriteData, dec_out[20], Clk);
+	register32 reg_21 (reg21, WriteData, dec_out[21], Clk);
+	register32 reg_22 (reg22, WriteData, dec_out[22], Clk);
+	register32 reg_23 (reg23, WriteData, dec_out[23], Clk);
+	register32 reg_24 (reg24, WriteData, dec_out[24], Clk);
+	register32 reg_25 (reg25, WriteData, dec_out[25], Clk);
+	register32 reg_26 (reg26, WriteData, dec_out[26], Clk);
+	register32 reg_27 (reg27, WriteData, dec_out[27], Clk);
+	register32 reg_28 (reg28, WriteData, dec_out[28], Clk);
+	register32 reg_29 (reg29, WriteData, dec_out[29], Clk);
+	register32 reg_30 (reg30, WriteData, dec_out[30], Clk);
+	register32 reg_31 (reg31, WriteData, dec_out[31], Clk);
+
+	//Data reading port 1
+	//Based on MUX with appropriate output, address, and inputs
+	mux32to1by32 mux1(
+	
+		ReadData1, ReadRegister1,
+		reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7,
+		reg8, reg9, reg10, reg11, reg12, reg13, reg14, reg15,
+		reg16, reg17, reg18, reg19, reg20, reg21, reg22, reg23,
+		reg24, reg25, reg26, reg27, reg28, reg29, reg30, reg31
+	);
+
+
+	//Data reading port 2
+	//Based on MUX with appropriate output, address, and inputs
+	mux32to1by32 mux2(
+	
+		ReadData2, ReadRegister2,
+		reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7,
+		reg8, reg9, reg10, reg11, reg12, reg13, reg14, reg15,
+		reg16, reg17, reg18, reg19, reg20, reg21, reg22, reg23,
+		reg24, reg25, reg26, reg27, reg28, reg29, reg30, reg31
+	);
 
+	
 endmodule
\ No newline at end of file
diff --git a/register.v b/register.v
index dc9b8cb..e100ad4 100644
--- a/register.v
+++ b/register.v
@@ -14,4 +14,38 @@ input		clk
         end
     end
 
+endmodule
+
+
+// 32-bit D Flip Flop Register with Enable
+// Positive edfe triggered
+module register32
+(
+output reg [31:0] q,
+input [31:0] d,
+input wrenable,
+input clk
+);
+
+	always @(posedge clk) begin
+		if(wrenable) begin
+			q[31:0]=d[31:0];
+		end
+	end
+endmodule
+
+
+
+// 32-bit Register that always outputs 0
+// register does not have write capability
+module register32zero
+(
+output reg [31:0] q,
+input [31:0] d,
+input wrenable,
+input clk
+);
+	always @(posedge clk) begin
+		q = 32'b0;
+	end
 endmodule
\ No newline at end of file