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Description
MRE:
module SpinTrue = {
proc spin() = {
while (true) {
}
}
}.
module SpinFalse = {
proc spin() = {
while (false) {
}
}
}.
equiv L: SpinFalse.spin ~ SpinTrue.spin:
true ==> true.
proof.
proc.
async while [predT,1] [predT,1] true true: (false) => //.
qed.
Deriving false from L:
require import AllCore.
lemma LF &m: Pr[SpinFalse.spin()@&m:true]=1%r.
proof. byphoare => //; proc; rcondf 1 => //. qed.
lemma LT &m: Pr[SpinTrue .spin()@&m:true]=0%r.
proof. byphoare => //; proc; hoare; while (true) => //. qed.
lemma F: false.
suff//: forall &m, 1%r = 0%r.
move => &m.
rewrite -(LF &m) -(LT &m).
byequiv L => //.
qed.
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