From f3ec0d2984cfe065dcc3b7d692030e19e5d353bc Mon Sep 17 00:00:00 2001 From: Carl Mattatall Date: Sat, 22 Nov 2025 17:08:16 -0600 Subject: [PATCH 1/3] [am263p4] fix bug in soc_rcm On higher optimization levels, instruction reordering can occur across boundary of reading peripheral clock div register --- source/drivers/soc/am263px/soc_rcm.c | 34 ++++++++++++++-------------- 1 file changed, 17 insertions(+), 17 deletions(-) diff --git a/source/drivers/soc/am263px/soc_rcm.c b/source/drivers/soc/am263px/soc_rcm.c index e2e5f67807..0fb7503059 100644 --- a/source/drivers/soc/am263px/soc_rcm.c +++ b/source/drivers/soc/am263px/soc_rcm.c @@ -195,7 +195,7 @@ const SOC_RcmClkSrcInfo gCLKOUTClkSrcInfoMap = * @details * Mapping Array between Clock mode and Clock Mode Value for MCAN */ -static uint16_t gMcanClkSrcValMap[] = +static const uint16_t gMcanClkSrcValMap[] = { [SOC_RcmPeripheralClockSource_XTALCLK] = 0x666U, [SOC_RcmPeripheralClockSource_SYS_CLK] = 0x222U, @@ -218,7 +218,7 @@ static uint16_t gMcanClkSrcValMap[] = * @details * Mapping Array between Clock mode and Clock Mode Value for OSPI */ -static uint16_t gOspiClkSrcValMap[] = +static const uint16_t gOspiClkSrcValMap[] = { [SOC_RcmPeripheralClockSource_XTALCLK] = 0x666U, [SOC_RcmPeripheralClockSource_SYS_CLK] = 0x222U, @@ -241,7 +241,7 @@ static uint16_t gOspiClkSrcValMap[] = * @details * Mapping Array between Clock mode and Clock Mode Value for RTI */ -static uint16_t gRtiClkSrcValMap[] = +static const uint16_t gRtiClkSrcValMap[] = { [SOC_RcmPeripheralClockSource_XTALCLK] = 0x666U, [SOC_RcmPeripheralClockSource_SYS_CLK] = 0x222U, @@ -264,7 +264,7 @@ static uint16_t gRtiClkSrcValMap[] = * @details * Mapping Array between Clock mode and Clock Mode Value for WDT */ -static uint16_t gWdtClkSrcValMap[] = +static const uint16_t gWdtClkSrcValMap[] = { [SOC_RcmPeripheralClockSource_XTALCLK] = 0x666U, [SOC_RcmPeripheralClockSource_SYS_CLK] = 0x222U, @@ -287,7 +287,7 @@ static uint16_t gWdtClkSrcValMap[] = * @details * Mapping Array between Clock mode and Clock Mode Value for McSPI */ -static uint16_t gMcSpiClkSrcValMap[] = +static const uint16_t gMcSpiClkSrcValMap[] = { [SOC_RcmPeripheralClockSource_XTALCLK] = 0x666U, [SOC_RcmPeripheralClockSource_SYS_CLK] = 0x222U, @@ -310,7 +310,7 @@ static uint16_t gMcSpiClkSrcValMap[] = * @details * Mapping Array between Clock mode and Clock Mode Value for MMC */ -static uint16_t gMmcClkSrcValMap[] = +static const uint16_t gMmcClkSrcValMap[] = { [SOC_RcmPeripheralClockSource_XTALCLK] = 0x666U, [SOC_RcmPeripheralClockSource_SYS_CLK] = 0x222U, @@ -333,7 +333,7 @@ static uint16_t gMmcClkSrcValMap[] = * @details * Mapping Array between Clock mode and Clock Mode Value for ICSSM UART */ -static uint16_t gIcssmUartClkSrcValMap[] = +static const uint16_t gIcssmUartClkSrcValMap[] = { [SOC_RcmPeripheralClockSource_XTALCLK] = 0x666U, [SOC_RcmPeripheralClockSource_SYS_CLK] = 0x222U, @@ -356,7 +356,7 @@ static uint16_t gIcssmUartClkSrcValMap[] = * @details * Mapping Array between Clock mode and Clock Mode Value for CPTS */ -static uint16_t gCptsClkSrcValMap[] = +static const uint16_t gCptsClkSrcValMap[] = { [SOC_RcmPeripheralClockSource_XTALCLK] = 0x666U, [SOC_RcmPeripheralClockSource_SYS_CLK] = 0x222U, @@ -402,7 +402,7 @@ static uint16_t gCptsClkSrcValMap[] = * @details * Mapping Array between Clock mode and Clock Mode Value for ControlSS PLL */ -static uint16_t gControlssPllClkSrcValMap[] = +static const uint16_t gControlssPllClkSrcValMap[] = { [SOC_RcmPeripheralClockSource_XTALCLK] = 0x666U, [SOC_RcmPeripheralClockSource_SYS_CLK] = UNSUPPORTED_CLOCK_SOURCE, @@ -425,7 +425,7 @@ static uint16_t gControlssPllClkSrcValMap[] = * @details * Mapping Array between Clock mode and Clock Mode Value for I2C */ -static uint16_t gI2cClkSrcValMap[] = +static const uint16_t gI2cClkSrcValMap[] = { [SOC_RcmPeripheralClockSource_XTALCLK] = 0x666U, [SOC_RcmPeripheralClockSource_SYS_CLK] = 0x222U, @@ -448,7 +448,7 @@ static uint16_t gI2cClkSrcValMap[] = * @details * Mapping Array between Clock mode and Clock Mode Value for LIN */ -static uint16_t gLinUartClkSrcValMap[] = +static const uint16_t gLinUartClkSrcValMap[] = { [SOC_RcmPeripheralClockSource_XTALCLK] = 0x666U, [SOC_RcmPeripheralClockSource_SYS_CLK] = 0x222U, @@ -471,7 +471,7 @@ static uint16_t gLinUartClkSrcValMap[] = * @details * Mapping Array between Clock mode and Clock Mode Value for R5F and SYSCLK */ -static uint16_t gR5SysClkSrcValMap[] = +static const uint16_t gR5SysClkSrcValMap[] = { [SOC_RcmPeripheralClockSource_XTALCLK] = UNSUPPORTED_CLOCK_SOURCE, [SOC_RcmPeripheralClockSource_SYS_CLK] = UNSUPPORTED_CLOCK_SOURCE, @@ -494,7 +494,7 @@ static uint16_t gR5SysClkSrcValMap[] = * @details * Mapping Array between Clock mode and Clock Mode Value for Trace */ -static uint16_t gTraceClkSrcValMap[] = +static const uint16_t gTraceClkSrcValMap[] = { [SOC_RcmPeripheralClockSource_XTALCLK] = 0x666U, [SOC_RcmPeripheralClockSource_SYS_CLK] = UNSUPPORTED_CLOCK_SOURCE, @@ -517,7 +517,7 @@ static uint16_t gTraceClkSrcValMap[] = * @details * Mapping Array between Clock mode and Clock Mode Value for CLKOUT */ -static uint16_t gClkoutClkSrcValMap[] = +static const uint16_t gClkoutClkSrcValMap[] = { [SOC_RcmPeripheralClockSource_XTALCLK] = 0x666U, [SOC_RcmPeripheralClockSource_SYS_CLK] = UNSUPPORTED_CLOCK_SOURCE, @@ -540,7 +540,7 @@ static uint16_t gClkoutClkSrcValMap[] = * @details * Mapping Array between Reset Cause Bit and Reset Cause */ -static SOC_RcmResetCause gResetBitToResetCause[12U] = +static cosnt SOC_RcmResetCause gResetBitToResetCause[12U] = { SOC_RcmResetCause_POWER_ON_RESET, SOC_RcmResetCause_WARM_RESET, @@ -869,7 +869,7 @@ static uint32_t SBL_rcmIsDualCoreSwitchSupported(uint32_t cpuId) */ static void SOC_rcmGetClkSrcAndDivReg (SOC_RcmPeripheralId periphId, SOC_RcmPeripheralClockSource clkSource, - uint16_t *clkSrcVal, + volatile uint16_t *clkSrcVal, volatile uint32_t **clkSrcReg, volatile uint32_t **clkdDivReg) { @@ -2066,7 +2066,7 @@ int32_t SOC_rcmSetPeripheralClock (SOC_RcmPeripheralId periphId, uint32_t freqHz) { volatile uint32_t *ptrClkSrcReg, *ptrClkDivReg; - uint16_t clkSrcVal; + volatile uint16_t clkSrcVal; uint32_t clkDivisor; int32_t retVal; uint32_t Finp; From c8df7d64bb7d7ca2ffb7210bdbf314c2ab395851 Mon Sep 17 00:00:00 2001 From: Carl Mattatall Date: Sat, 22 Nov 2025 17:10:06 -0600 Subject: [PATCH 2/3] [am263p] fix bug in soc_rcm On higher optimization levels, instruction reordering can occur across boundary of reading peripheral clock div register --- source/drivers/soc/am263x/soc_rcm.c | 36 ++++++++++++++--------------- 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/source/drivers/soc/am263x/soc_rcm.c b/source/drivers/soc/am263x/soc_rcm.c index 5f91214501..90b8e9ce72 100644 --- a/source/drivers/soc/am263x/soc_rcm.c +++ b/source/drivers/soc/am263x/soc_rcm.c @@ -195,7 +195,7 @@ const SOC_RcmClkSrcInfo gCLKOUTClkSrcInfoMap = * @details * Mapping Array between Clock mode and Clock Mode Value for MCAN */ -static uint16_t gMcanClkSrcValMap[] = +static const uint16_t gMcanClkSrcValMap[] = { [SOC_RcmPeripheralClockSource_XTALCLK] = 0x666U, [SOC_RcmPeripheralClockSource_SYS_CLK] = 0x222U, @@ -218,7 +218,7 @@ static uint16_t gMcanClkSrcValMap[] = * @details * Mapping Array between Clock mode and Clock Mode Value for QSPI */ -static uint16_t gQspiClkSrcValMap[] = +static const uint16_t gQspiClkSrcValMap[] = { [SOC_RcmPeripheralClockSource_XTALCLK] = 0x666U, [SOC_RcmPeripheralClockSource_SYS_CLK] = 0x222U, @@ -241,7 +241,7 @@ static uint16_t gQspiClkSrcValMap[] = * @details * Mapping Array between Clock mode and Clock Mode Value for RTI */ -static uint16_t gRtiClkSrcValMap[] = +static const uint16_t gRtiClkSrcValMap[] = { [SOC_RcmPeripheralClockSource_XTALCLK] = 0x666U, [SOC_RcmPeripheralClockSource_SYS_CLK] = 0x222U, @@ -264,7 +264,7 @@ static uint16_t gRtiClkSrcValMap[] = * @details * Mapping Array between Clock mode and Clock Mode Value for WDT */ -static uint16_t gWdtClkSrcValMap[] = +static const uint16_t gWdtClkSrcValMap[] = { [SOC_RcmPeripheralClockSource_XTALCLK] = 0x666U, [SOC_RcmPeripheralClockSource_SYS_CLK] = 0x222U, @@ -287,7 +287,7 @@ static uint16_t gWdtClkSrcValMap[] = * @details * Mapping Array between Clock mode and Clock Mode Value for McSPI */ -static uint16_t gMcSpiClkSrcValMap[] = +static const uint16_t gMcSpiClkSrcValMap[] = { [SOC_RcmPeripheralClockSource_XTALCLK] = 0x666U, [SOC_RcmPeripheralClockSource_SYS_CLK] = 0x222U, @@ -310,7 +310,7 @@ static uint16_t gMcSpiClkSrcValMap[] = * @details * Mapping Array between Clock mode and Clock Mode Value for MMC */ -static uint16_t gMmcClkSrcValMap[] = +static const uint16_t gMmcClkSrcValMap[] = { [SOC_RcmPeripheralClockSource_XTALCLK] = 0x666U, [SOC_RcmPeripheralClockSource_SYS_CLK] = 0x222U, @@ -333,7 +333,7 @@ static uint16_t gMmcClkSrcValMap[] = * @details * Mapping Array between Clock mode and Clock Mode Value for ICSSM UART */ -static uint16_t gIcssmUartClkSrcValMap[] = +static const uint16_t gIcssmUartClkSrcValMap[] = { [SOC_RcmPeripheralClockSource_XTALCLK] = 0x666U, [SOC_RcmPeripheralClockSource_SYS_CLK] = 0x222U, @@ -356,7 +356,7 @@ static uint16_t gIcssmUartClkSrcValMap[] = * @details * Mapping Array between Clock mode and Clock Mode Value for CPTS */ -static uint16_t gCptsClkSrcValMap[] = +static const uint16_t gCptsClkSrcValMap[] = { [SOC_RcmPeripheralClockSource_XTALCLK] = 0x666U, [SOC_RcmPeripheralClockSource_SYS_CLK] = 0x222U, @@ -379,7 +379,7 @@ static uint16_t gCptsClkSrcValMap[] = * @details * Mapping Array between Clock mode and Clock Mode Value for GPMC */ -static uint16_t gGpmcClkSrcValMap[] = +static const uint16_t gGpmcClkSrcValMap[] = { [SOC_RcmPeripheralClockSource_XTALCLK] = 0x666U, [SOC_RcmPeripheralClockSource_SYS_CLK] = 0x222U, @@ -402,7 +402,7 @@ static uint16_t gGpmcClkSrcValMap[] = * @details * Mapping Array between Clock mode and Clock Mode Value for ControlSS PLL */ -static uint16_t gControlssPllClkSrcValMap[] = +static const uint16_t gControlssPllClkSrcValMap[] = { [SOC_RcmPeripheralClockSource_XTALCLK] = 0x666U, [SOC_RcmPeripheralClockSource_SYS_CLK] = UNSUPPORTED_CLOCK_SOURCE, @@ -425,7 +425,7 @@ static uint16_t gControlssPllClkSrcValMap[] = * @details * Mapping Array between Clock mode and Clock Mode Value for I2C */ -static uint16_t gI2cClkSrcValMap[] = +static const uint16_t gI2cClkSrcValMap[] = { [SOC_RcmPeripheralClockSource_XTALCLK] = 0x666U, [SOC_RcmPeripheralClockSource_SYS_CLK] = 0x222U, @@ -448,7 +448,7 @@ static uint16_t gI2cClkSrcValMap[] = * @details * Mapping Array between Clock mode and Clock Mode Value for LIN */ -static uint16_t gLinUartClkSrcValMap[] = +static const uint16_t gLinUartClkSrcValMap[] = { [SOC_RcmPeripheralClockSource_XTALCLK] = 0x666U, [SOC_RcmPeripheralClockSource_SYS_CLK] = 0x222U, @@ -471,7 +471,7 @@ static uint16_t gLinUartClkSrcValMap[] = * @details * Mapping Array between Clock mode and Clock Mode Value for R5F and SYSCLK */ -static uint16_t gR5SysClkSrcValMap[] = +static const uint16_t gR5SysClkSrcValMap[] = { [SOC_RcmPeripheralClockSource_XTALCLK] = UNSUPPORTED_CLOCK_SOURCE, [SOC_RcmPeripheralClockSource_SYS_CLK] = UNSUPPORTED_CLOCK_SOURCE, @@ -494,7 +494,7 @@ static uint16_t gR5SysClkSrcValMap[] = * @details * Mapping Array between Clock mode and Clock Mode Value for Trace */ -static uint16_t gTraceClkSrcValMap[] = +static const uint16_t gTraceClkSrcValMap[] = { [SOC_RcmPeripheralClockSource_XTALCLK] = 0x666U, [SOC_RcmPeripheralClockSource_SYS_CLK] = UNSUPPORTED_CLOCK_SOURCE, @@ -517,7 +517,7 @@ static uint16_t gTraceClkSrcValMap[] = * @details * Mapping Array between Clock mode and Clock Mode Value for CLKOUT */ -static uint16_t gClkoutClkSrcValMap[] = +static const uint16_t gClkoutClkSrcValMap[] = { [SOC_RcmPeripheralClockSource_XTALCLK] = 0x666U, [SOC_RcmPeripheralClockSource_SYS_CLK] = UNSUPPORTED_CLOCK_SOURCE, @@ -540,7 +540,7 @@ static uint16_t gClkoutClkSrcValMap[] = * @details * Mapping Array between Reset Cause Bit and Reset Cause */ -static SOC_RcmResetCause gResetBitToResetCause[12U] = +static const SOC_RcmResetCause gResetBitToResetCause[12U] = { SOC_RcmResetCause_POWER_ON_RESET, SOC_RcmResetCause_WARM_RESET, @@ -869,7 +869,7 @@ static uint32_t SBL_rcmIsDualCoreSwitchSupported(uint32_t cpuId) */ static void SOC_rcmGetClkSrcAndDivReg (SOC_RcmPeripheralId periphId, SOC_RcmPeripheralClockSource clkSource, - uint16_t *clkSrcVal, + volatile uint16_t *clkSrcVal, volatile uint32_t **clkSrcReg, volatile uint32_t **clkdDivReg) { @@ -2030,7 +2030,7 @@ int32_t SOC_rcmSetPeripheralClock (SOC_RcmPeripheralId periphId, uint32_t freqHz) { volatile uint32_t *ptrClkSrcReg, *ptrClkDivReg; - uint16_t clkSrcVal; + uint16_t volatile clkSrcVal; uint32_t clkDivisor; int32_t retVal; uint32_t Finp; From 2c284741b4154198c90bac70f92a26e6355dd402 Mon Sep 17 00:00:00 2001 From: Carl Mattatall Date: Sat, 22 Nov 2025 17:47:52 -0600 Subject: [PATCH 3/3] [dpl] support yieldable log processing --- source/kernel/dpl/DebugP.h | 25 +++++++++++ .../nortos/dpl/common/DebugP_shmLogReader.c | 41 ++++++++++++++++--- 2 files changed, 61 insertions(+), 5 deletions(-) diff --git a/source/kernel/dpl/DebugP.h b/source/kernel/dpl/DebugP.h index 896bab964d..a4f2925189 100644 --- a/source/kernel/dpl/DebugP.h +++ b/source/kernel/dpl/DebugP.h @@ -92,6 +92,16 @@ extern "C" { */ #define DebugP_SHM_LOG_IS_VALID (0x12345678U) + +/** \brief Infinite read chunk size for the shared memory reader + * + * DebugP_shmLogReaderSetChunkSize(DebugP_SHM_LOG_READER_CHUNK_SIZE_INF) + * will make DebugP_shmLogRead() process the entire shared memory log in one go + * or until the end of the shared memory log is reached. + */ +#define DebugP_SHM_LOG_READER_CHUNK_SIZE_INF UINT16_MAX + + /** * Macro defines the value of two */ @@ -323,11 +333,26 @@ void DebugP_uartLogWriterPutChar(char character); * * The parameter `shmLog` is a array and is indexed using core ID as defined by \ref CSL_CoreID * + * A single invocation processes up to DebugP_shmLogReaderGetChunkSize() log lines + * * \param shmLog [in] Array of addresses of shared memory where the reader should read from. * \param numCores [in] Number of entries in the shmLog array. Typically \ref CSL_CORE_ID_MAX */ void DebugP_shmLogReaderInit(DebugP_ShmLog *shmLog, uint16_t numCores); +/** \brief Set the read chunk size for the shared memory reader + * + * \param readChunkSize [in] The read chunk size in bytes. + */ +void DebugP_shmLogReaderSetChunkSize(uint16_t readChunkSize); + + +/** \brief Get the read chunk size for the shared memory reader + * + * \return The read chunk size in bytes. + */ +uint16_t DebugP_shmLogReaderGetChunkSize(void); + /** * \brief Reads logs from shared memory. * diff --git a/source/kernel/nortos/dpl/common/DebugP_shmLogReader.c b/source/kernel/nortos/dpl/common/DebugP_shmLogReader.c index 1af8d696b5..0db5f97b41 100755 --- a/source/kernel/nortos/dpl/common/DebugP_shmLogReader.c +++ b/source/kernel/nortos/dpl/common/DebugP_shmLogReader.c @@ -38,12 +38,19 @@ #define DEBUG_SHM_LOG_READER_LINE_BUF_SIZE (130u) typedef struct { - uint8_t isCoreShmLogInialized[CSL_CORE_ID_MAX]; - DebugP_ShmLog *shmLog; uint8_t numCores; - char lineBuf[DEBUG_SHM_LOG_READER_LINE_BUF_SIZE+UNSIGNED_INTEGERVAL_THREE]; /* +3 to add \r\n and null char at end of string in worst case */ + /* + * Support yieldable log processing so user can return and perform other tasks e.g. petting watchdog + * + * This is useful in scenarios when: + * - Other cores produce logs at a faster rate than the reader can consume them + * - The reader has other tasks to perform e.g. petting watchdog, servicing I/O, etc + */ + uint16_t chunkSize; + DebugP_ShmLog *shmLog; + char lineBuf[DEBUG_SHM_LOG_READER_LINE_BUF_SIZE+UNSIGNED_INTEGERVAL_THREE]; /* +3 to add \r\n and null char at end of string in worst case */ } DebugP_ShmLogReaderCtrl; DebugP_ShmLogReaderCtrl gDebugShmLogReaderCtrl; @@ -66,10 +73,21 @@ void DebugP_shmLogReaderInit(DebugP_ShmLog *shmLog, uint16_t numCores) } gDebugShmLogReaderCtrl.shmLog = shmLog; gDebugShmLogReaderCtrl.numCores = (uint8_t)numCores; + gDebugShmLogReaderCtrl.chunkSize = DebugP_SHM_LOG_READER_CHUNK_SIZE_INF; DebugP_shmLogReaderTaskCreate(); } + +void DebugP_shmLogReaderSetChunkSize(uint16_t chunkSize){ + gDebugShmLogReaderCtrl.chunkSize = chunkSize; +} + + +uint16_t DebugP_shmLogReaderGetChunkSize(void){ + return gDebugShmLogReaderCtrl.chunkSize; +} + uint32_t DebugP_shmLogReaderGetString(DebugP_ShmLog *shmLog, char *buf, uint32_t buf_size) { @@ -163,8 +181,10 @@ uint32_t DebugP_shmLogReaderGetString(DebugP_ShmLog *shmLog, void DebugP_shmLogRead(void) { uint32_t i; - - for(i=0; i= gDebugShmLogReaderCtrl.chunkSize){ + /* Save core index so next invocation we resume log processing from the current core */ + coreIndex = i; + return; + } + } } while(strLen != 0U); } } + /* All logs processed without exceeding chunk size - reset core index to start from the beginning next invocation */ + coreIndex = 0; } void DebugP_shmLogReaderTaskMain(void *args)