[BUG] Latest release fails to build on vivado step #512
Description
📋 Bug Summary
Brief Description:
Severity Level:
- Critical - System crashes, data loss, or complete failure
- [ X] High - Major functionality broken, significant impact
- Medium - Minor functionality issues, workarounds available
- Low - Cosmetic issues, minor inconveniences
📦 Environment Details
Run help_ticket.sh and give the output
🚨 Problem Description
What happened?
Error Messages/Logs:
<!-- Paste relevant error messages, stack traces, or log outputs here -->
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[kruesephiikz@megacity-x8664 PCILeechFWGenerator]$ sudo ~/.pcileech-venv/bin/python3 pcileech.py build --bdf 0000:03:00.0 --board pcileech_enigma_x1 --device-type network --vivado-path /opt/Xilinx/2025.2/Vivado/
09:46:28 │ INFO │ [VFIO] Rebuilding VFIO constants for current kernel...
09:46:28 │ INFO │ [VFIO] VFIO constants rebuilt successfully
09:46:28 │ INFO │ Discovering boards from pcileech-fpga repository...
09:46:28 │ INFO │ [BUILD] No datastore found; running host collect now
09:46:28 │ INFO │ [BUILD] Stage 1: Collecting device data on host (VFIO operations enabled)
09:46:28 │ INFO │ [COLLECT] Read 4096 bytes of config space
09:46:28 │ INFO │ [CFG64] 0000: 69 19 b1 e0 03 00 10 00 10 00 00 02 10 00 00 00
09:46:28 │ INFO │ [CFG64] 0010: 04 00 50 ad 00 00 00 00 01 30 00 00 00 00 00 00
09:46:28 │ INFO │ [CFG64] 0020: 00 00 00 00 00 00 00 00 00 00 00 00 62 14 77 12
09:46:28 │ INFO │ [CFG64] 0030: 00 00 00 00 40 00 00 00 00 00 00 00 ff 01 00 00
09:46:28 │ INFO │ [PCICAP] MSI-X capability not found
09:46:28 │ INFO │ [COLLECT] Wrote /home/kruesephiikz/PCILeechFWGenerator/pcileech_datastore/device_context.json
09:46:28 │ INFO │ [COLLECT] Wrote /home/kruesephiikz/PCILeechFWGenerator/pcileech_datastore/msix_data.json
09:46:28 │ INFO │ [BUILD] Host collect complete → /home/kruesephiikz/PCILeechFWGenerator/pcileech_datastore
09:46:28 │ INFO │ [BUILD] Stage 2: Template generation from collected device data
======================================================================
Template Generation Mode Selection
======================================================================
Container runtime available: podman
Two execution modes are available:
[C] Container mode (recommended)
✓ Isolated environment
✓ Reproducible builds
✓ No system dependency conflicts
✗ Slightly slower startup
[L] Local mode
✓ Faster execution
✓ Direct access to system
✗ May have dependency conflicts
✗ Less reproducible
======================================================================
Select mode [C/L] (default: Container): c
09:46:31 │ INFO │ [BUILD] Using container mode with podman (VFIO not needed - using host data)
09:46:31 │ INFO │ [BUILD] Using existing container image: pcileech-fwgen
09:46:31 │ INFO │ [BUILD] Container will use preloaded device context from host
09:46:31 │ INFO │ [BUILD] Executing in container using podman
Info: Skipping VFIO/module operations (host-context-only or unsupported container environment)
14:46:32 │ INFO │ [VFIO_DECISION] VFIO operations skipped (using preloaded device data)
14:46:32 │ INFO │ [HOST_CFG] Loaded preloaded config space from host: 4096 bytes
14:46:32 │ INFO │ [BUILD] Using preloaded config space from host: 4096 bytes
14:46:32 │ INFO │ [FALLBACK] Marked 26 variables as critical (no fallbacks)
14:46:32 │ INFO │ [PCIL] Initializing PCILeech generator for device 0000:03:00.0
14:46:32 │ INFO │ [PCIL] Generator received preloaded config space: 4096 bytes
14:46:32 │ INFO │ [SV_GEN] SystemVerilogGenerator initialized successfully
14:46:32 │ INFO │ [PCIL] PCILeech generator components initialized successfully
14:46:32 │ INFO │ [BUILD] ➤ Starting template_validation...
14:46:32 │ INFO │ [TEMPLATE] Validating board: pcileech_enigma_x1
14:46:32 │ WARNING│ [TEMPLATE] Board directory not found: pcileech_enigma_x1
14:46:32 │ WARNING│ [TEMPLATE] Board template validation failed - build may fail
14:46:32 │ INFO │ [BUILD] ➤ Completed template_validation
14:46:32 │ INFO │ [BUILD] ➤ Starting host_context_check...
14:46:32 │ INFO │ [BUILD] ➤ Completed host_context_check
14:46:32 │ INFO │ [BUILD] ➤ Starting firmware_generation...
14:46:32 │ INFO │ [MSIX] MSI-X preload: host-context-only mode active; skipping sysfs/VFIO
14:46:32 │ INFO │ [BUILD] ➤ Generating PCILeech firmware …
14:46:32 │ INFO │ [PCIL] Behavior profiling disabled, skipping device behavior capture
14:46:32 │ INFO │ [CFG] Analyzing configuration space for device 0000:03:00.0
14:46:32 │ INFO │ [CFG] Using pre-collected configuration space data from host
14:46:32 │ INFO │ [SUBS] Subsystem ID extraction - Vendor: 0x1462, Device: 0x1277
14:46:32 │ INFO │ [SUBS] Subsystem IDs differ from main IDs - Main: 0x1969:0xe0b1, Subsystem: 0x1462:0x1277
14:46:32 │ INFO │ [CNFG] Starting BAR extraction from config space (4096 bytes)
14:46:32 │ INFO │ [BARX] BAR 0 size from sysfs: 262144 bytes (256.0KB)
14:46:32 │ INFO │ [BARX] BAR 2 size from sysfs: 128 bytes (128B)
14:46:32 │ INFO │ [BARX] Completed BAR extraction: found 2 active BARs
14:46:32 │ INFO │ [INFO] Successfully extracted device information:
14:46:32 │ INFO │ [INFO] Vendor ID: 0x1969
14:46:32 │ INFO │ [INFO] Device ID: 0xe0b1
14:46:32 │ INFO │ [INFO] Class Code: 0x020000
14:46:32 │ INFO │ [INFO] Revision ID: 0x10
14:46:32 │ INFO │ [INFO] Command: 0x0003
14:46:32 │ INFO │ [INFO] Status: 0x0010
14:46:32 │ INFO │ [INFO] Header Type: 0x00
14:46:32 │ INFO │ [INFO] Subsystem Vendor: 0x1462
14:46:32 │ INFO │ [INFO] Subsystem Device: 0x1277
14:46:32 │ INFO │ [INFO] Cache Line Size: 16
14:46:32 │ INFO │ [INFO] Latency Timer: 0
14:46:32 │ INFO │ [INFO] BIST: 0x00
14:46:32 │ INFO │ [INFO] Total BARs found: 2
14:46:32 │ INFO │ [BARS] Active BARs found: 2
14:46:32 │ INFO │ [BARS] BAR 0: memory @ 0x00000000ad500000 (64-bit, non-prefetchable, size=0x40000)
14:46:32 │ INFO │ [BARS] BAR 2: io @ 0x0000000000003000 (32-bit, non-prefetchable, size=0x80)
14:46:32 │ INFO │ [DEVI] Extracted device info: vendor=1969 device=e0b1 class=020000
14:46:32 │ INFO │ [LOOKUP] Pre-fallback device_info (shape): {'command': 'str', 'status': 'str', 'cache_line_size': 'str', 'latency_timer': 'str', 'header_type': 'str', 'bist': 'str'}
14:46:32 │ INFO │ [LOOKUP] Pre-fallback device_info (sanitized): {
"bist": "0",
"cache_line_size": "16",
"command": "3",
"header_type": "0",
"latency_timer": "0",
"status": "16"
}
14:46:32 │ INFO │ [CFG] Configuration space processed: VID=6505, DID=57521, Class=131072
14:46:32 │ INFO │ [MSIX] Preloading MSI-X data from sysfs before VFIO binding
14:46:32 │ INFO │ [PCICAP] MSI-X capability not found
14:46:32 │ INFO │ [MSIX] No MSI-X capability found during preload
14:46:32 │ INFO │ [PCIL] Building comprehensive template context
14:46:32 │ INFO │ Building context for 0000:03:00.0 with none
14:46:32 │ INFO │ [PWR] Waking device from D3hot
14:46:32 │ INFO │ [BAR] ╔═════════════════════════════════════════════════════════════╗
14:46:32 │ INFO │ [BAR] ║ BASE ADDRESS REGISTER DISCOVERY & ANALYSIS ║
14:46:32 │ INFO │ [BAR] ╠═════════════════════════════════════════════════════════════╣
14:46:32 │ INFO │ Starting VFIO device fd acquisition for 0000:03:00.0
14:46:32 │ INFO │ [VFIO] Device 0000:03:00.0 is in IOMMU group 20
14:46:32 │ WARNING│ [VFIO] [WARN] ensure_device_vfio_binding called: 0000:03:00.0 already bound to vfio-pci (re-check, not a rebind)
14:46:32 │ INFO │ [VFIO] VFIO binding recheck passed for 0000:03:00.0 (IOMMU group 20)
14:46:32 │ INFO │ [VFIO] Device 0000:03:00.0 bound to VFIO group 20
14:46:32 │ INFO │ [BAR] ║ BAR0 @ 0xAD500000 │ 256.00 KB │ 64-bit │ MEM ║
14:46:32 │ INFO │ Starting VFIO device fd acquisition for 0000:03:00.0
14:46:32 │ INFO │ [VFIO] Device 0000:03:00.0 is in IOMMU group 20
14:46:32 │ WARNING│ [VFIO] [WARN] ensure_device_vfio_binding called: 0000:03:00.0 already bound to vfio-pci (re-check, not a rebind)
14:46:32 │ INFO │ [VFIO] VFIO binding recheck passed for 0000:03:00.0 (IOMMU group 20)
14:46:32 │ INFO │ [VFIO] Device 0000:03:00.0 bound to VFIO group 20
14:46:32 │ INFO │ [BAR] ╠═════════════════════════════════════════════════════════════╣
14:46:32 │ INFO │ [BAR] ║ DISCOVERED: 1/2 BARs │ MEMORY MAPPED: 0.25 MB ║
14:46:32 │ INFO │ [BAR] ╚═════════════════════════════════════════════════════════════╝
14:46:32 │ INFO │ [BAR] Primary BAR: index=0, size=0.25MB
14:46:32 │ WARNING│ [SYSFS_BAR] Failed to enable memory decoding: [Errno 30] Read-only file system: '/sys/bus/pci/devices/0000:03:00.0/enable'
14:46:32 │ ERROR │ BAR read requires root privileges (for mmap)
14:46:32 │ WARNING│ [SYSFS_BAR] BAR sampling requires root privileges; skipping direct sampling
14:46:32 │ WARNING│ [MMIO] MMIO learning failed: [Errno 13] Permission denied: '.pcileech_cache'
14:46:32 │ WARNING│ Device profile '1969_e0b1' not found, using live device detection
14:46:32 │ INFO │ [PCIL] Building board configuration for pcileech_enigma_x1
14:46:32 │ INFO │ Discovering boards from pcileech-fpga repository...
14:46:32 │ INFO │ [BOARDS] Discovered 11 boards from submodule
14:46:32 │ INFO │ Discovered 11 boards
14:46:32 │ INFO │ [PCIL] Board configuration loaded: xc7a75tfgg484-2
14:46:32 │ INFO │ [PCIL] Loaded board XDC content for pcileech_enigma_x1 (6606 bytes)
14:46:32 │ INFO │ [PCI_CAP] Loaded 21 default rules
14:46:32 │ INFO │ [PCI_CAP] Discovered 6 capabilities
14:46:32 │ WARNING│ [VFIO] [WARN] ensure_device_vfio_binding called: 0000:03:00.0 already bound to vfio-pci (re-check, not a rebind)
14:46:32 │ INFO │ [VFIO] VFIO binding recheck passed for 0000:03:00.0 (IOMMU group 20)
14:46:32 │ INFO │ [PCIL] Context built successfully: 1969:e0b1:10
14:46:32 │ INFO │ [PCIL] Template context built successfully with 54 top-level keys
14:46:32 │ INFO │ Generating SystemVerilog modules
14:46:32 │ ERROR │ [VALID] Device has class_code=020000 (Ethernet Controller). If the source device is NOT an Ethernet controller, this indicates a fallback value was used instead of reading from hardware. This will cause incorrect device enumeration in Windows/Linux.
14:46:32 │ ERROR │ [VALID] Device has class_code=020000 (Ethernet Controller). If the source device is NOT an Ethernet controller, this indicates a fallback value was used instead of reading from hardware. This will cause incorrect device enumeration in Windows/Linux.
14:46:32 │ WARNING│ [TEMPLATING] Device serial number unavailable; cfg_dsn will default to 0
14:46:32 │ INFO │ [SV_GEN] Generating configuration space overlay
14:46:32 │ INFO │ [SV_GEN] Generating device-specific write mask overlay
14:46:32 │ INFO │ [WRITEMASK] Generating writemask from /tmp/tmp347h748m.coe
14:46:32 │ INFO │ [WRITEMASK] Found 0 capabilities (0 std, 1 ext)
14:46:32 │ INFO │ [WRITEMASK] Writemask generated: tmptnpe2bp4.coe
14:46:32 │ INFO │ [SV_GEN] Generated writemask overlay (9707 bytes)
14:46:32 │ INFO │ [SV_GEN] Generated BAR controller (10976 bytes, generic impl)
14:46:32 │ INFO │ [SV_GEN] Generated 3 overlay files
14:46:32 │ INFO │ [PCIL] Generated 3 SystemVerilog modules | msix init_len=0 entries=0
14:46:32 │ INFO │ Generating additional firmware components
14:46:32 │ INFO │ [PCIL] Copying XDC constraint files for board pcileech_enigma_x1 from submodule
14:46:32 │ INFO │ [PCIL] Copied constraint file: pcileech_enigma_x1.xdc
14:46:32 │ INFO │ [PCIL] Copied 1 XDC constraint files from submodule
14:46:32 │ INFO │ [PCIL] Copying static TCL scripts for board pcileech_enigma_x1 from voltcyclone-fpga submodule
14:46:32 │ INFO │ [FILEMGR] Copying Vivado TCL scripts for board: pcileech_enigma_x1
14:46:32 │ INFO │ [FILEMGR] Copied TCL script: vivado_flash.tcl
14:46:32 │ INFO │ [FILEMGR] Copied TCL script: vivado_build.tcl
14:46:32 │ INFO │ [FILEMGR] Copied TCL script: vivado_generate_project.tcl
14:46:32 │ INFO │ [FILEMGR] Successfully copied 3 TCL scripts
14:46:32 │ INFO │ [PCIL] Copying IP files for board pcileech_enigma_x1 from voltcyclone-fpga
14:46:32 │ INFO │ [FILEMGR] Copied IP file: pcileech_cfgspace.coe
14:46:32 │ INFO │ [FILEMGR] Copied IP file: pcileech_bar_zero4k.coe
14:46:32 │ INFO │ [FILEMGR] Copied IP file: pcileech_cfgspace_writemask.coe
14:46:32 │ INFO │ [FILEMGR] Copied IP file: fifo_1_1_clk2.xci
14:46:32 │ INFO │ [FILEMGR] Copied IP file: fifo_64_64_clk2_comrx.xci
14:46:32 │ INFO │ [FILEMGR] Copied IP file: fifo_134_134_clk2_rxfifo.xci
14:46:32 │ INFO │ [FILEMGR] Copied IP file: fifo_64_64.xci
14:46:32 │ INFO │ [FILEMGR] Copied IP file: fifo_74_74_clk1_bar_rd1.xci
14:46:32 │ INFO │ [FILEMGR] Copied IP file: fifo_32_32_clk1_comtx.xci
14:46:32 │ INFO │ [FILEMGR] Copied IP file: drom_pcie_cfgspace_writemask.xci
14:46:32 │ INFO │ [FILEMGR] Copied IP file: bram_bar_zero4k.xci
14:46:32 │ INFO │ [FILEMGR] Copied IP file: fifo_129_129_clk1.xci
14:46:32 │ INFO │ [FILEMGR] Copied IP file: pcie_7x_0.xci
14:46:32 │ INFO │ [FILEMGR] Copied IP file: bram_pcie_cfgspace.xci
14:46:32 │ INFO │ [FILEMGR] Copied IP file: fifo_141_141_clk1_bar_wr.xci
14:46:32 │ INFO │ [FILEMGR] Copied IP file: fifo_32_32_clk2.xci
14:46:32 │ INFO │ [FILEMGR] Copied IP file: fifo_64_64_clk1_fifocmd.xci
14:46:32 │ INFO │ [FILEMGR] Copied IP file: fifo_43_43_clk2.xci
14:46:32 │ INFO │ [FILEMGR] Copied IP file: fifo_134_134_clk1_bar_rdrsp.xci
14:46:32 │ INFO │ [FILEMGR] Copied IP file: fifo_34_34.xci
14:46:32 │ INFO │ [FILEMGR] Copied IP file: fifo_134_134_clk2.xci
14:46:32 │ INFO │ [FILEMGR] Copied IP file: fifo_256_32_clk2_comtx.xci
14:46:32 │ INFO │ [FILEMGR] Copied IP file: fifo_49_49_clk2.xci
14:46:32 │ INFO │ [FILEMGR] Successfully copied 23 IP files
14:46:32 │ INFO │ [PCIL] Copied 26 files from submodule (TCL + IP)
14:46:32 │ INFO │ [HEX] Generating configuration space hex file
14:46:32 │ INFO │ [HEX] Generated configuration space hex file with 4096 bytes
14:46:32 │ INFO │ [WRMASK] Generating writemask COE file
14:46:32 │ INFO │ [WRMASK] Config space COE not found, generating it first
14:46:32 │ INFO │ [WRMASK] Used cached config space COE content at /datastore/output/src/pcileech_cfgspace.coe
14:46:32 │ INFO │ [WRITEMASK] Generating writemask from /datastore/output/src/pcileech_cfgspace.coe
14:46:32 │ INFO │ [WRITEMASK] Found 0 capabilities (0 std, 1 ext)
14:46:32 │ INFO │ [WRITEMASK] Writemask generated: pcileech_cfgspace_writemask.coe
14:46:32 │ WARNING│ [PCIL] Missing expected overlay files: ['pcileech_cfgspace']
14:46:32 │ INFO │ [PCIL] PCILeech firmware generation completed successfully
14:46:32 │ INFO │ [BUILD] ➤ Completed firmware_generation
14:46:32 │ INFO │ [BUILD] ➤ Starting module_writing...
14:46:32 │ INFO │ [BUILD] ➤ Writing SystemVerilog modules …
14:46:32 │ INFO │ [BUILD] Wrote 1 SystemVerilog modules: pcileech_tlps128_bar_controller.sv
14:46:32 │ INFO │ [BUILD] ➤ Completed module_writing
14:46:32 │ INFO │ [BUILD] ➤ Starting profile_generation...
14:46:32 │ INFO │ [BUILD] ➤ Generating behavior profile …
14:46:32 │ INFO │ [BUILD] Profiling disabled (host-context-only mode)
14:46:32 │ INFO │ [BUILD] ➤ Completed profile_generation
14:46:32 │ INFO │ [BUILD] ➤ Starting tcl_generation...
14:46:32 │ INFO │ [BUILD] ➤ Generating TCL scripts …
14:46:32 │ INFO │ [FILEMGR] Created PCILeech directory structure
14:46:32 │ INFO │ [FILEMGR] Source directory: /datastore/output/src
14:46:32 │ INFO │ [FILEMGR] IP directory: /datastore/output/ip
14:46:32 │ INFO │ [FILEMGR] Using PCILeech repository at: /app/lib/voltcyclone-fpga
14:46:32 │ INFO │ [FILEMGR] Board path: /app/lib/voltcyclone-fpga/EnigmaX1
14:46:32 │ INFO │ [FILEMGR] Copied source file: pcileech_com.sv
14:46:32 │ INFO │ [FILEMGR] Copied source file: pcileech_tlps128_bar_controller.sv
14:46:32 │ INFO │ [FILEMGR] Copied source file: pcileech_pcie_a7.sv
14:46:32 │ INFO │ [FILEMGR] Copied source file: pcileech_pcie_tlp_a7.sv
14:46:32 │ INFO │ [FILEMGR] Copied source file: pcileech_mux.sv
14:46:32 │ INFO │ [FILEMGR] Copied source file: pcileech_tlps128_cfgspace_shadow.sv
14:46:32 │ INFO │ [FILEMGR] Copied source file: pcileech_fifo.sv
14:46:32 │ INFO │ [FILEMGR] Copied source file: pcileech_ft601.sv
14:46:32 │ INFO │ [FILEMGR] Copied source file: pcileech_pcie_cfg_a7.sv
14:46:32 │ INFO │ [FILEMGR] Copied source file: pcileech_enigma_x1_top.sv
14:46:32 │ INFO │ [FILEMGR] Copied header file: pcileech_header.svh
14:46:32 │ INFO │ [FILEMGR] Copied constraint file: pcileech_enigma_x1.xdc
14:46:32 │ INFO │ [FILEMGR] Successfully copied 12 PCILeech source files
14:46:32 │ INFO │ [FILEMGR] Copying Vivado TCL scripts for board: pcileech_enigma_x1
14:46:32 │ INFO │ [FILEMGR] Copied TCL script: vivado_flash.tcl
14:46:32 │ INFO │ [FILEMGR] Copied TCL script: vivado_build.tcl
14:46:32 │ INFO │ [FILEMGR] Copied TCL script: vivado_generate_project.tcl
14:46:32 │ INFO │ [FILEMGR] Successfully copied 3 TCL scripts
14:46:32 │ INFO │ [BUILD] • Copied 3 Vivado TCL scripts from submodule
14:46:32 │ INFO │ [BUILD] ➤ Completed tcl_generation
14:46:32 │ INFO │ [BUILD] ➤ Starting constraint_writing...
14:46:32 │ INFO │ [BUILD] Wrote XDC constraints file: pcileech_enigma_x1.xdc (6606 bytes)
14:46:32 │ INFO │ [BUILD] ➤ Completed constraint_writing
14:46:32 │ INFO │ [BUILD] ➤ Starting device_info_saving...
14:46:32 │ INFO │ [BUILD] ➤ Saving device information …
14:46:32 │ INFO │ [BUILD] Writing JSON file: device_info.json
14:46:32 │ INFO │ [BUILD] Successfully wrote JSON file: device_info.json
14:46:32 │ INFO │ [BUILD] ➤ Completed device_info_saving
14:46:32 │ INFO │ [BUILD] ➤ Starting post_build_validation...
14:46:32 │ INFO │ [BUILD] ➤ Running post-build validation …
14:46:32 │ INFO │ [VALID] Running post-build validation checks
14:46:32 │ INFO │ [VALID] Post-build validation PASSED - all checks successful
14:46:32 │ INFO │ [VALID] Validation Report: 0 errors, 0 warnings, 18 info
14:46:32 │ INFO │ [VALID] All critical checks passed (18 checks)
14:46:32 │ INFO │ [BUILD] Writing JSON file: validation_report.json
14:46:32 │ INFO │ [BUILD] Successfully wrote JSON file: validation_report.json
14:46:32 │ INFO │ [BUILD] ➤ Completed post_build_validation
14:46:32 │ INFO │ [BUILD] ➤ Starting manifest_saving...
14:46:32 │ INFO │ [FILEMGR] Saved file manifest: 0 files, 0 bytes, 0 duplicates skipped
14:46:32 │ INFO │ [BUILD] ➤ Completed manifest_saving
14:46:32 │ INFO │ Build finished in 0.2 s ✓
14:46:32 │ INFO │ [SUMMARY]
Generated artifacts in /datastore/output
14:46:32 │ INFO │ [SUMMARY]
SystemVerilog modules (10):
14:46:32 │ INFO │ [SUMMARY] - src/pcileech_com.sv
14:46:32 │ INFO │ [SUMMARY] - src/pcileech_enigma_x1_top.sv
14:46:32 │ INFO │ [SUMMARY] - src/pcileech_fifo.sv
14:46:32 │ INFO │ [SUMMARY] - src/pcileech_ft601.sv
14:46:32 │ INFO │ [SUMMARY] - src/pcileech_mux.sv
14:46:32 │ INFO │ [SUMMARY] - src/pcileech_pcie_a7.sv
14:46:32 │ INFO │ [SUMMARY] - src/pcileech_pcie_cfg_a7.sv
14:46:32 │ INFO │ [SUMMARY] - src/pcileech_pcie_tlp_a7.sv
14:46:32 │ INFO │ [SUMMARY] - src/pcileech_tlps128_bar_controller.sv
14:46:32 │ INFO │ [SUMMARY] - src/pcileech_tlps128_cfgspace_shadow.sv
14:46:32 │ INFO │ [SUMMARY]
TCL scripts (3):
14:46:32 │ INFO │ [SUMMARY] - vivado_build.tcl
14:46:32 │ INFO │ [SUMMARY] - vivado_flash.tcl
14:46:32 │ INFO │ [SUMMARY] - vivado_generate_project.tcl
14:46:32 │ INFO │ [SUMMARY]
JSON files (4):
14:46:32 │ INFO │ [SUMMARY] - device_info.json
14:46:32 │ INFO │ [SUMMARY] - file_manifest.json
14:46:32 │ INFO │ [SUMMARY] - template_context_keys.json
14:46:32 │ INFO │ [SUMMARY] - validation_report.json
14:46:32 │ INFO │ [SUMMARY]
Other files (27):
14:46:32 │ INFO │ [SUMMARY] - constraints/pcileech_enigma_x1.xdc
14:46:32 │ INFO │ [SUMMARY] - ip/bram_bar_zero4k.xci
14:46:32 │ INFO │ [SUMMARY] - ip/bram_pcie_cfgspace.xci
14:46:32 │ INFO │ [SUMMARY] - ip/drom_pcie_cfgspace_writemask.xci
14:46:32 │ INFO │ [SUMMARY] - ip/fifo_129_129_clk1.xci
14:46:32 │ INFO │ [SUMMARY] - ip/fifo_134_134_clk1_bar_rdrsp.xci
14:46:32 │ INFO │ [SUMMARY] - ip/fifo_134_134_clk2.xci
14:46:32 │ INFO │ [SUMMARY] - ip/fifo_134_134_clk2_rxfifo.xci
14:46:32 │ INFO │ [SUMMARY] - ip/fifo_141_141_clk1_bar_wr.xci
14:46:32 │ INFO │ [SUMMARY] - ip/fifo_1_1_clk2.xci
14:46:32 │ INFO │ [SUMMARY] - ip/fifo_256_32_clk2_comtx.xci
14:46:32 │ INFO │ [SUMMARY] - ip/fifo_32_32_clk1_comtx.xci
14:46:32 │ INFO │ [SUMMARY] - ip/fifo_32_32_clk2.xci
14:46:32 │ INFO │ [SUMMARY] - ip/fifo_34_34.xci
14:46:32 │ INFO │ [SUMMARY] - ip/fifo_43_43_clk2.xci
14:46:32 │ INFO │ [SUMMARY] - ip/fifo_49_49_clk2.xci
14:46:32 │ INFO │ [SUMMARY] - ip/fifo_64_64.xci
14:46:32 │ INFO │ [SUMMARY] - ip/fifo_64_64_clk1_fifocmd.xci
14:46:32 │ INFO │ [SUMMARY] - ip/fifo_64_64_clk2_comrx.xci
14:46:32 │ INFO │ [SUMMARY] - ip/fifo_74_74_clk1_bar_rd1.xci
14:46:32 │ INFO │ [SUMMARY] - ip/pcie_7x_0.xci
14:46:32 │ INFO │ [SUMMARY] - ip/pcileech_bar_zero4k.coe
14:46:32 │ INFO │ [SUMMARY] - ip/pcileech_cfgspace.coe
14:46:32 │ INFO │ [SUMMARY] - ip/pcileech_cfgspace_writemask.coe
14:46:32 │ INFO │ [SUMMARY] - src/pcileech_cfgspace.coe
14:46:32 │ INFO │ [SUMMARY] - src/pcileech_cfgspace_writemask.coe
14:46:32 │ INFO │ [SUMMARY] - src/pcileech_header.svh
14:46:32 │ INFO │ [SUMMARY]
Total: 44 files
09:46:33 │ INFO │ [VIVADO] IP artifact repair complete → dirs=1 locks=0 files=20
09:46:33 │ INFO │ [VIVADO] Starting Vivado build for board: pcileech_enigma_x1
09:46:33 │ INFO │ [VIVADO] Output directory: /home/kruesephiikz/PCILeechFWGenerator/pcileech_datastore/output
09:46:33 │ WARNING│ [VIVADO] Failed to use integrated build; falling back to generated scripts: voltcyclone-fpga at /home/kruesephiikz/PCILeechFWGenerator/lib/voltcyclone-fpga is not a valid git repository.
Remediation: git submodule update --init --recursive
****** Vivado v2025.2 (64-bit)
**** SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
**** IP Build 6300035 on Fri Nov 14 10:48:45 MST 2025
**** SharedData Build 6298862 on Thu Nov 13 04:50:51 MST 2025
**** Start of session at: Thu Dec 25 09:46:34 2025
** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
** Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
source /home/kruesephiikz/PCILeechFWGenerator/pcileech_datastore/output/vivado_build.tcl
# puts "-------------------------------------------------------"
-------------------------------------------------------
# puts " GENERATING IP CORES. "
GENERATING IP CORES.
# puts "-------------------------------------------------------"
-------------------------------------------------------
# puts "Checking IP core status..."
Checking IP core status...
# report_ip_status -name ip_status -file ip_status_report.txt
ERROR: [Common 17-53] User Exception: No open project. Please create or open a project before executing this command.
INFO: [Common 17-206] Exiting Vivado at Thu Dec 25 09:46:36 2025...
Error report written to: /home/kruesephiikz/PCILeechFWGenerator/pcileech_datastore/output/error_report.txt
============================================================
VIVADO BUILD SUMMARY
============================================================
⚠ 2 warning(s) found
⚠ Build completed with warnings
============================================================
Build failed: Vivado build failed with return code 1. See error report: ================================================================================
VIVADO BUILD ERROR REPORT
================================================================================
Generated: 2025-12-25 09:46:36
SUMMARY:
⚠ Warnings: 2
WARNINGS:
----------------------------------------
1. ℹ INFO: Exiting Vivado at Thu Dec 25 09:46:36 2025...
🏷 Type: Unknown
📝 Raw: INFO: [Common 17-206] Exiting Vivado at Thu Dec 25 09:46:36 2025...
2. ℹ INFO: Exiting Vivado at Thu Dec 25 09:46:36 2025...
🏷 Type: Unknown
📝 Raw: INFO: [Common 17-206] Exiting Vivado at Thu Dec 25 09:46:36 2025...
ERROR TYPE BREAKDOWN:
----------------------------------------
Unknown: 2 warnings
================================================================================
Steps to Reproduce:
Command Line Used:
# Paste the exact command(s) that triggered the issueConfiguration Details:
🎯 Expected Behavior
What should happen instead?
Reference Implementation:
🔬 Additional Context
Frequency:
- Always reproducible
- Intermittent (occurs sometimes)
- Rare (occurred once or twice)
Impact Assessment:
- Blocks development/testing
- Affects firmware functionality
- Synthesis/build failures
- Runtime errors
- Performance issues
Workaround Available:
- Yes (please describe below)
- No
Workaround Description:
📎 Attachments
Required Files:
-
config.json(sanitized) -
generate.logor relevant log files - Error screenshots or terminal output
Optional Files:
- Custom
.tclfiles - Custom
.svfiles - Synthesis reports
- Waveform captures
- Core dump files
🛠️ Debugging Information
Commands Run for Debugging:
# List any debugging commands you tried
# e.g., python pcileech.py --verbose, vivado -version, etc.System Information:
# Output of system info commands (optional)
# e.g., uname -a, python --version, pip list | grep -i pci✅ Pre-submission Checklist
I have:
- Checked that I'm using the latest version from the main branch
- Searched for existing similar issues
- Read the relevant documentation/wiki pages
- Included all required information above
- Removed any sensitive/personal information
- Tested with minimal reproduction case
- Verified this isn't a configuration issue
Module-specific checks (if applicable):
-
device_emulator- Checked device configuration and capabilities -
cap_parser- Verified PCI capability parsing -
svgen- Checked SystemVerilog generation -
flash- Verified flash operations and board connectivity -
vfio- Checked VFIO driver binding and permissions
🏷️ Labels
Issue Type:
- Synthesis Error
- Runtime Error
- Configuration Issue
- Documentation Issue
- Feature Request
- Performance Issue
Component:
- Core Generator
- Device Emulation
- Capability Parser
- SystemVerilog Generation
- Flash Operations
- VFIO Integration
- TUI Interface
- Build System