Redeclaration-is-error was fixed in #1273

tautschnig · tautschnig · commit 05f4ee264ef4 · 2025-09-26T09:47:59.000Z
diff --git a/regression/verilog/modules/input_and_ansi_input.desc b/regression/verilog/modules/input_and_ansi_input.desc
@@ -1,8 +1,7 @@
-KNOWNBUG
+CORE
 input_and_ansi_input.v
 
 ^EXIT=2$
 ^SIGNAL=0$
 --
 --
-The redeclaration must be errored.
