Merge pull request #1317 from diffblue/function_ports3

Verilog: test for function ports

Author: tautschnig

regression/verilog/functioncall/function_ports3.desc

@@ -0,0 +1,8 @@
+CORE
+function_ports3.sv
+--module main
+^EXIT=0$
+^SIGNAL=0$
+--
+^warning: ignoring
+--

regression/verilog/functioncall/function_ports3.sv

@@ -0,0 +1,11 @@
+module main;
+
+  function [7:0] identity(input [7:0] value);
+    identity = value;
+  endfunction
+
+  // function ports are 'assignment-like contexts', 1800-2017 10.8,
+  // and hence, the signed argument is sign extended
+  assert final(identity(1'sb1) == 8'hff);
+
+endmodule