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Merge pull request #1492 from diffblue/expr2verilog-struct
Verilog: format struct expressions
2 parents e12ebb5 + 90aefcc commit 48db68f

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3 files changed

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regression/verilog/expressions/static_cast4.desc

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@@ -1,6 +1,7 @@
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CORE
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static_cast4.sv
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--module main
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^\[.*\] struct packed'\('\{ a: 1, b: 2 \}\) == main\.some_struct: PROVED .*$
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^EXIT=0$
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^SIGNAL=0$
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--

src/verilog/expr2verilog.cpp

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@@ -1540,6 +1540,43 @@ expr2verilogt::resultt expr2verilogt::convert_sequence_property_instance(
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/*******************************************************************\
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Function: expr2verilogt::convert_struct
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Inputs:
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Outputs:
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Purpose:
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\*******************************************************************/
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expr2verilogt::resultt expr2verilogt::convert_struct(const struct_exprt &src)
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{
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std::string dest = "'{";
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auto &type = to_struct_type(src.type());
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DATA_INVARIANT(
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type.components().size() == src.operands().size(),
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"number of compontents must match");
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for(std::size_t index = 0; index < src.operands().size(); index++)
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{
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auto &op = src.operands()[index];
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if(index != 0)
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dest += ',';
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dest += ' ';
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dest += id2string(type.components()[index].get_name());
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dest += ": ";
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dest += convert_rec(op).s;
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}
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dest += " }";
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return {verilog_precedencet::MAX, dest};
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}
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/*******************************************************************\
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Function: expr2verilogt::convert_value_range
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Inputs:
@@ -2081,6 +2118,11 @@ expr2verilogt::resultt expr2verilogt::convert_rec(const exprt &src)
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to_sva_sequence_property_instance_expr(src));
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}
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else if(src.id() == ID_struct)
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{
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return convert_struct(to_struct_expr(src));
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}
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// no VERILOG language expression for internal representation
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return convert_norep(src);
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}

src/verilog/expr2verilog_class.h

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@@ -187,6 +187,8 @@ class expr2verilogt
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resultt convert_sequence_property_instance(
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const class sva_sequence_property_instance_exprt &);
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resultt convert_struct(const struct_exprt &);
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protected:
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const namespacet &ns;
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};

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