Merge pull request #606 from diffblue/use_verilog_module_source

Verilog typechecker now uses verilog_module_sourcet

Author: tautschnig

src/verilog/verilog_expr.h

@@ -1893,9 +1893,14 @@ to_verilog_assume_statement(verilog_statementt &statement)
 class verilog_module_sourcet : public irept
 {
 public:
-  irep_idt name() const
+  irep_idt base_name() const
+  {
+    return get(ID_base_name);
+  }
+
+  void base_name(irep_idt base_name)
   {
-    return get(ID_name);
+    return set(ID_base_name, base_name);
   }
 
   using parameter_port_listt = verilog_parameter_declt::declaratorst;
@@ -1930,10 +1935,15 @@ class verilog_module_sourcet : public irept
     return (module_itemst &)(add(ID_module_items).get_sub());
   }
 
-  const source_locationt &source_location()
+  const source_locationt &source_location() const
   {
     return static_cast<const source_locationt &>(find(ID_C_source_location));
   }
+
+  source_locationt &add_source_location()
+  {
+    return static_cast<source_locationt &>(add(ID_C_source_location));
+  }
 };
 
 inline const verilog_module_sourcet &to_verilog_module_source(const irept &irep)

src/verilog/verilog_module.h

@@ -9,9 +9,7 @@ Author: Daniel Kroening, kroening@kroening.com
 #ifndef CPROVER_VERILOG_MODULE_H
 #define CPROVER_VERILOG_MODULE_H
 
-#include <string>
-
-#include <util/expr.h>
+#include "verilog_expr.h"
 
 struct verilog_modulet
 {
@@ -20,14 +18,15 @@ struct verilog_modulet
   exprt ports;
   exprt module_items;
   source_locationt location;
-  
-  irept to_irep() const
+
+  verilog_module_sourcet to_irep() const
   {
-    irept irep;
-    irep.set(ID_name, name);
+    verilog_module_sourcet irep;
+    irep.base_name(name);
     irep.add(ID_parameter_port_list) = parameter_port_list;
     irep.add(ID_ports)=ports;
     irep.add(ID_module_items) = module_items;
+    irep.add_source_location() = location;
     return irep;
   }
 

src/verilog/verilog_typecheck.cpp

@@ -1837,7 +1837,7 @@ bool verilog_typecheck(
   verilog_parse_treet::module_mapt::const_iterator it=
     parse_tree.module_map.find(
       id2string(verilog_module_name(module)));
-    
+
   if(it==parse_tree.module_map.end())
   {
     messaget message(message_handler);
@@ -1848,7 +1848,7 @@ bool verilog_typecheck(
 
   return verilog_typecheck(
     symbol_table,
-    it->second->verilog_module,
+    it->second->verilog_module.to_irep(),
     parse_tree.standard,
     message_handler);
 }
@@ -1867,25 +1867,23 @@ Function: verilog_typecheck
 
 bool verilog_typecheck(
   symbol_table_baset &symbol_table,
-  const verilog_modulet &verilog_module,
+  const verilog_module_sourcet &verilog_module_source,
   verilog_standardt standard,
   message_handlert &message_handler)
 {
   // create symbol
 
-  symbolt symbol;
+  irep_idt base_name = verilog_module_source.base_name();
+
+  symbolt symbol{verilog_module_symbol(base_name), module_typet{}, ID_Verilog};
 
-  symbol.mode=ID_Verilog;
-  symbol.base_name=verilog_module.name;
-  symbol.type=module_typet();
-  symbol.name=verilog_module_symbol(verilog_module.name);
-  symbol.base_name=verilog_module.name;
-  symbol.pretty_name=verilog_module.name;
+  symbol.base_name = base_name;
+  symbol.pretty_name = base_name;
   symbol.module=symbol.name;
-  symbol.location=verilog_module.location;
+  symbol.location = verilog_module_source.source_location();
+
+  symbol.type.add(ID_module_source) = verilog_module_source;
 
-  symbol.type.add(ID_module_source)=verilog_module.to_irep();
-  
   // put symbol in symbol_table
 
   symbolt *new_symbol;

src/verilog/verilog_typecheck.h

@@ -27,7 +27,7 @@ bool verilog_typecheck(
 
 bool verilog_typecheck(
   symbol_table_baset &,
-  const verilog_modulet &verilog_module,
+  const verilog_module_sourcet &verilog_module_source,
   verilog_standardt,
   message_handlert &message_handler);