SystemVerilog: concurrent assertion items go into module namespace

Concurrent assertion items (assert/assume/cover) that are module items with
a block label go into the module name space, not into a separate "property"
name space.

Assertion items without block item now get a label based on the kind of the
assertion item (assert/assume/cover).

Author: kroening

regression/ebmc/BDD/BDD2.desc

@@ -3,6 +3,6 @@ BDD2.sv
 --module main --bdd
 ^EXIT=10$
 ^SIGNAL=0$
-^\[main.property.my_prop1\] always main.counter < 199: PROVED$
-^\[main.property.my_prop2\] always main.counter < 198: REFUTED$
+^\[main\.my_prop1\] always main.counter < 199: PROVED$
+^\[main\.my_prop2\] always main.counter < 198: REFUTED$
 --

regression/ebmc/BDD/BDD3.desc

@@ -3,6 +3,6 @@ BDD3.sv
 --module main --bdd
 ^EXIT=10$
 ^SIGNAL=0$
-^\[main.property.my_prop1\] always main.counter <= 10: PROVED$
-^\[main.property.my_prop2\] always main.counter < 10: REFUTED$
+^\[main\.my_prop1\] always main\.counter <= 10: PROVED$
+^\[main\.my_prop2\] always main\.counter < 10: REFUTED$
 --

regression/ebmc/BDD/BDD_SVA1.desc

@@ -3,14 +3,14 @@ BDD_SVA1.sv
 --bdd
 ^EXIT=10$
 ^SIGNAL=0$
-^\[top\.property\.p0\] always top\.my_bit: PROVED$
-^\[top\.property\.p1\] always top\.my_bit: PROVED$
-^\[top\.property\.p2\] always \(top\.counter == 3 \|-> \(nexttime top\.counter == 4\)\): FAILURE: property not supported by BDD engine$
-^\[top\.property\.p3\] always \(top\.counter == 3 \|=> top\.counter == 4\): FAILURE: property not supported by BDD engine$
-^\[top\.property\.p4\] always \(top\.counter == 3 \|=> \(nexttime top\.counter == 5\)\): FAILURE: property not supported by BDD engine$
-^\[top\.property\.p5\] always s_eventually top\.counter == 8: PROVED$
-^\[top\.property\.p6\] always \(top\.counter == 0 \|-> \(s_eventually top\.counter == 8\)\): FAILURE: property not supported by BDD engine$
-^\[top\.property\.p7\] always \(top\.counter == 0 \|-> \(top\.counter <= 5 until top\.counter == 6\)\): FAILURE: property not supported by BDD engine$
-^\[top\.property\.p8\] always \(top\.counter == 0 \|-> \(top\.counter <= 5 until_with top\.counter == 5\)\): FAILURE: property not supported by BDD engine$
+^\[top\.p0\] always top\.my_bit: PROVED$
+^\[top\.p1\] always top\.my_bit: PROVED$
+^\[top\.p2\] always \(top\.counter == 3 \|-> \(nexttime top\.counter == 4\)\): FAILURE: property not supported by BDD engine$
+^\[top\.p3\] always \(top\.counter == 3 \|=> top\.counter == 4\): FAILURE: property not supported by BDD engine$
+^\[top\.p4\] always \(top\.counter == 3 \|=> \(nexttime top\.counter == 5\)\): FAILURE: property not supported by BDD engine$
+^\[top\.p5\] always s_eventually top\.counter == 8: PROVED$
+^\[top\.p6\] always \(top\.counter == 0 \|-> \(s_eventually top\.counter == 8\)\): FAILURE: property not supported by BDD engine$
+^\[top\.p7\] always \(top\.counter == 0 \|-> \(top\.counter <= 5 until top\.counter == 6\)\): FAILURE: property not supported by BDD engine$
+^\[top\.p8\] always \(top\.counter == 0 \|-> \(top\.counter <= 5 until_with top\.counter == 5\)\): FAILURE: property not supported by BDD engine$
 --
 ^warning: ignoring

regression/ebmc/Next-in-Property1/test.desc

@@ -3,5 +3,5 @@ main.sv
 --module top --bound 10
 ^EXIT=0$
 ^SIGNAL=0$
-^\[top.property.p1\] always \(top.counter\[0\] |-> \(##1 top.counter <= 5\)\): SUCCESS$
+^\[top\.p1\] always \(top\.counter\[0\] |-> \(##1 top\.counter <= 5\)\): SUCCESS$
 --

regression/ebmc/SVA-LTL/freeze.desc

@@ -1,8 +1,8 @@
 CORE
 freeze.sv
 --bound 1
-^\[main\.property\.p1\] always s_eventually main\.w: REFUTED$
-^\[main\.property\.p2\] always s_eventually !main\.w: REFUTED$
+^\[main\.p1\] always s_eventually main\.w: REFUTED$
+^\[main\.p2\] always s_eventually !main\.w: REFUTED$
 ^EXIT=10$
 ^SIGNAL=0$
 --

regression/ebmc/SVA-LTL/lasso1-counterexample.desc

@@ -3,7 +3,7 @@ lasso1.sv
 --bound 10 --waveform
 ^EXIT=10$
 ^SIGNAL=0$
-^\[top\.property\.p0\] .* REFUTED$
+^\[top\.p0\] .* REFUTED$
 ^             0  1  2  3  4  5  6  7  8  9 10$
 ^top\.counter  0  1  2  3  4  5  6  7  8  9  3$
 --

regression/ebmc/SVA-LTL/lasso1-small-bound.desc

@@ -3,6 +3,6 @@ lasso1.sv
 --bound 5
 ^EXIT=0$
 ^SIGNAL=0$
-^\[top\.property\.p0\] .* PROVED up to bound 5$
+^\[top\.p0\] .* PROVED up to bound 5$
 --
 --

regression/ebmc/SVA-LTL/simple_counterexamples_to_Fp.p0.desc

@@ -1,8 +1,8 @@
 CORE
 simple_counterexamples_to_Fp.sv
---bound 10 --property top.property.p0
+--bound 10 --property top.p0
 ^Adding lasso constraints$
 ^EXIT=10$
 ^SIGNAL=0$
-^\[top\.property\.p0\] .* REFUTED$
+^\[top\.p0\] .* REFUTED$
 --

regression/ebmc/SVA-LTL/simple_counterexamples_to_Fp.p1.desc

@@ -1,8 +1,8 @@
 CORE
 simple_counterexamples_to_Fp.sv
---bound 10 --property top.property.p1
+--bound 10 --property top.p1
 ^Adding lasso constraints$
 ^EXIT=10$
 ^SIGNAL=0$
-^\[top\.property\.p1\] .* REFUTED$
+^\[top\.p1\] .* REFUTED$
 --

regression/ebmc/SVA-LTL/simple_counterexamples_to_Fp.p2.desc

@@ -1,8 +1,8 @@
 CORE
 simple_counterexamples_to_Fp.sv
---bound 10 --property top.property.p2
+--bound 10 --property top.p2
 ^Adding lasso constraints$
 ^EXIT=10$
 ^SIGNAL=0$
-^\[top\.property\.p2\] .* REFUTED$
+^\[top\.p2\] .* REFUTED$
 --