Merge pull request #1498 from diffblue/typedef_name_collision3

Verilog: test for name collision between typedef and module instance

Author: tautschnig

regression/verilog/typedef/typedef_name_collision3.desc

@@ -0,0 +1,7 @@
+CORE
+typedef_name_collision3.sv
+
+^file .* line 11: duplicate definition of identifier `some_identifier' in module `main'$
+^EXIT=2$
+^SIGNAL=0$
+--

regression/verilog/typedef/typedef_name_collision3.sv

@@ -0,0 +1,13 @@
+module sub;
+
+
+endmodule
+
+module main;
+
+  wire some_identifier;
+
+  // name collision
+  sub some_identifier();
+
+endmodule