We read every piece of feedback, and take your input very seriously.
To see all available qualifiers, see our documentation.
There was an error while loading. Please reload this page.
2 parents b5fc8e4 + 3efeaf6 commit 9732d42Copy full SHA for 9732d42
regression/verilog/SVA/cycle_delay_star2.desc
@@ -0,0 +1,10 @@
1
+KNOWNBUG
2
+cycle_delay_star2.sv
3
+--bound 10
4
+^\[main.p0\] ##\[\*\] main\.x == 4: REFUTED$
5
+^EXIT=10$
6
+^SIGNAL=0$
7
+--
8
+^warning: ignoring
9
10
+The BMC engine gives the wrong answer.
regression/verilog/SVA/cycle_delay_star2.sv
@@ -0,0 +1,14 @@
+module main(input clk);
+
+ reg [2:0] x;
+ initial x=0;
+ // 0, 1, 2, 3, 3, ...
+ always @(posedge clk)
+ if(x<=3) x++;
11
+ // fails -- 4 is never reached
12
+ initial p0: assert property (##[*] x==4);
13
14
+endmodule
0 commit comments