Merge pull request #975 from diffblue/default_disable1

SVA: KNOWNBUG test for `default disable iff`

Author: tautschnig

regression/verilog/SVA/default_disable1.desc

@@ -0,0 +1,8 @@
+KNOWNBUG
+default_disable1.sv
+
+^EXIT=10$
+^SIGNAL=0$
+--
+^warning: ignoring
+--

regression/verilog/SVA/default_disable1.sv

@@ -0,0 +1,7 @@
+module main(input clock, reset);
+
+  default clocking cb @(posedge clk);
+  endclocking
+  default disable iff (!reset);
+
+endmodule