From 8e0705b9494ca9ad210429f1733285b32451d657 Mon Sep 17 00:00:00 2001
From: Daniel Kroening <dkr@amazon.com>
Date: Fri, 19 Dec 2025 06:51:14 -0800
Subject: [PATCH] Verilog: test for gate instantiation with multiple instances

---
 .../verilog/primitive_gates/multiple_instances1.desc   |  8 ++++++++
 .../verilog/primitive_gates/multiple_instances1.sv     | 10 ++++++++++
 2 files changed, 18 insertions(+)
 create mode 100644 regression/verilog/primitive_gates/multiple_instances1.desc
 create mode 100644 regression/verilog/primitive_gates/multiple_instances1.sv

diff --git a/regression/verilog/primitive_gates/multiple_instances1.desc b/regression/verilog/primitive_gates/multiple_instances1.desc
new file mode 100644
index 000000000..a6ad00a01
--- /dev/null
+++ b/regression/verilog/primitive_gates/multiple_instances1.desc
@@ -0,0 +1,8 @@
+CORE
+multiple_instances1.sv
+
+^EXIT=0$
+^SIGNAL=0$
+--
+^warning: ignoring
+--
diff --git a/regression/verilog/primitive_gates/multiple_instances1.sv b/regression/verilog/primitive_gates/multiple_instances1.sv
new file mode 100644
index 000000000..a6917e2f7
--- /dev/null
+++ b/regression/verilog/primitive_gates/multiple_instances1.sv
@@ -0,0 +1,10 @@
+module main;
+
+  wire w1, w2;
+
+  and a1(w1, 1, 1), a2(w2, 1, 0);
+
+  initial assert(w1==1);
+  initial assert(w2==0);
+
+endmodule