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Boundary Cases #162

@jeffsetter

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@jeffsetter

I was wondering if these outputs from Halide were valid in clockwork. And if they properly map to the FPGA (I already know that the CGRA has issues with these piecewise stores).

I specifically have concerns about:
hcompute_repeat_image_stencil->add_load("hw_input_global_wrapper_stencil", "63", "select(((64 <= repeat_image_s0_x) || (repeat_image_s0_x < 0)), (repeat_image_s0_x % 64), max(min(repeat_image_s0_x, 63), 0))");

and
hcompute_mirror_image_stencil->add_load("hw_input_global_wrapper_stencil", "0", "select(((64 <= mirror_image_s0_x) || (mirror_image_s0_x < 0)), min(select(((mirror_image_s0_x % 128) < 64),(mirror_image_s0_x % 128), (127 - (mirror_image_s0_x % 128))), 63), max(min(mirror_image_s0_x, 63), 0))");

Here are the full applications:
bc_const_compute.txt
bc_const_memory.txt
bc_repeat_compute.txt
bc_repeat_memory.txt
bc_mirror_compute.txt
bc_mirror_memory.txt

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