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Changes needed for the Lake area optimization #185

@jake-ke

Description

@jake-ke

Missing compute unit file:

  • test_glb/gaussian_isscc
  • test_glb/camera_pipeline_isscc
  • test_glb/unsharp_isscc
  • test_glb/resnet1
  • test_glb/resnet4_x
  • test_glb/resnet5_1
  • test_glb/resnet_5_x_new
  • test_glb/resnet_5_1_new
  • test_glb/resnet5_1_unroll_cyclic
  • test_glb/resnet_output_stationary_tiny
  • test_glb/resnet5_1_full
  • test_glb/resnet2_x_full_compute.json

Current Failed tests:

  • test_glb/resnet_init_unroll_tile (mismatch, init path needs to be prioritized)
  • test_glb/resnet_last (mismatch)
  • test_glb/resnet_3_1 (mismatch)
  • test_glb/resnet_5_x (does not generate the new config registers)
  • test_glb/resnet_5_1_unroll (mismatch)
  • test_glb/resnet5_1_unroll_cyclic (mismatch)
  • test_glb/resnet_output_stationary_small (mismatch)
  • test_glb/resnet_output_stationary_tiny (mismatch)
  • test_single_port_mem/matmul_unroll2 (mismatch, agg2sram write not prioritized) #188

Skipped Tests:

  • test_single_port_mem/nlmeans_simple_trunc (skip, tb size needs to be 4)
  • test_pond/nlmeans_simple (skip, tb size needs to be 4)
  • test_pond/three_level_pond_rolled (skip, in2agg dim = 4)

Clockwork changes TODO:

  • prioritize the initialization path in the update operation so that the Agg2Sram doing initialization will always write to SRAM right after it receives 4 words (refer to output bank 6 in resnet_init_unroll_tile)
  • (probably related to the issue above) prioritize Agg2Sram in normal operations so it writes SRAM right after it receives 4 words (refer to ub_hw_input_global_wrapper_stencil_BANK_0 in matmul_unroll2 )
  • linearize Agg2Sram read and write data strides (refer to camera_pipeline_2x2)
  • (probably related to the change above) remove Agg2Sram read_data_starting_addr and write_data_starting_addr as they should always be 0. Can also remove In2Agg write_data_starting_addr for the same reason
  • (optional): flatten In2Agg ID as much as possible (this is currently done in Lake and we are using maximum 3 ID levels)

Lake Changes:

  • update LakeTop wrapper with the options to configure and enable/disable the area optimizations
  • remove linearization pass in Lake once they are done in clockwork
  • (optional) remove flatten pass in Lake once they are done in clockwork

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