diff --git a/snippets/systemverilog.snippets b/snippets/systemverilog.snippets
index 828a6de9c..e07103357 100644
--- a/snippets/systemverilog.snippets
+++ b/snippets/systemverilog.snippets
@@ -1,32 +1,35 @@
 extends verilog
 
-# Foreach Loop
-snippet forea
+snippet tdsp "typedef struct packed"
+	typedef struct packed {
+		int ${2:data};
+	} ${1:`vim_snippets#Filename('$1_t', 'name')`};
+snippet tde "typedef enum"
+	typedef enum ${2:logic[15:0]}
+	{
+		${3:REG = 16'h0000}
+	} ${1:my_dest_t};
+snippet forea "Foreach Loop"
 	foreach (${1}) begin
 		${0}
 	end
-# Do-while statement
-snippet dowh
+snippet dowh "Do-while statement"
 	do begin
 		${0}
 	end while (${1});
-# Combinational always block
-snippet alc
+snippet alc "Combinational always block"
 	always_comb begin ${1:: statement_label}
 		${0}
 	end $1
-# Sequential logic
-snippet alff
+snippet alff "Sequential logic"
 	always_ff @(posedge ${1:clk}) begin ${2:: statement_label}
 		${0}
 	end $2
-# Latched logic
-snippet all
+snippet all "Latched logic"
 	always_latch begin ${1:: statement_label}
 		${0}
 	end $1
-# Class
-snippet cl
+snippet cl "Class"
 	class ${1:class_name};
 		// data or class properties
 		${0}
@@ -36,18 +39,15 @@ snippet cl
 		endfunction : new
 
 	endclass : $1
-# Typedef structure
-snippet types
+snippet types "Typedef structure"
 	typedef struct {
 		${0}
 	} ${1:name_t};
-# Program block
-snippet prog
+snippet prog "Program block"
 	program ${1:program_name} ();
 		${0}
 	endprogram : $1
-# Interface block
-snippet intf
+snippet intf "Interface block"
 	interface ${1:program_name} ();
 		// nets
 		${0}
@@ -56,18 +56,15 @@ snippet intf
 		// modports
 
 	endinterface : $1
-# Clocking Block
-snippet clock
+snippet clock "Clocking Block"
 	clocking ${1:clocking_name} @(${2:posedge} ${3:clk});
 		${0}
 	endclocking : $1
-# Covergroup construct
-snippet cg
+snippet cg "Covergroup construct"
 	covergroup ${1:group_name} @(${2:posedge} ${3:clk});
 		${0}
 	endgroup : $1
-# Package declaration
-snippet pkg
+snippet pkg "Package declaration"
 	package ${1:package_name};
 		${0}
 	endpackage : $1
diff --git a/snippets/verilog.snippets b/snippets/verilog.snippets
index 16bacc2a3..d33c534f0 100644
--- a/snippets/verilog.snippets
+++ b/snippets/verilog.snippets
@@ -1,99 +1,175 @@
-# if statement
-snippet if
+snippet . "IO when instantiating the module"
+	.${1:io_name}(${2:$1})
+snippet as "Assign"
+	assign ${1:name} = ${2:value};
+snippet be "Begin-end"
+	begin
+		${0:${VISUAL}}
+	end
+snippet cond "Conditional operator"
+	(${1:if}) ? ${2:then} : ${3:else};
+snippet fsm "Finite state machine"
+	localparam ${1:IDLE} = 0;
+	${2:/*other states*/}
+
+	reg [${3:n}:${4:0}] ${5:state}_reg, $5_next;
+	always @(posedge clk) begin
+		if (rst) begin
+			$5_reg <= $1;
+		end
+		else begin
+			$5_reg <= $5_next;
+		end
+	end
+
+	always @* begin
+		// default values, regardless of state
+
+		case ($5_reg)
+			$1: begin
+				${6:/* $1 behavior */}
+			end
+			default: begin
+				$5_next = $1;
+			end
+		encase
+	end
+snippet gen "Generate block"
+	generate
+		${0:${VISUAL}}
+	endgenerate
+snippet in "Input"
+	input ${1:input_name}_i
+snippet inst "Instantiate module"
+	${1:module_name} ${2:$1}_inst (${3:.*});
+snippet instp "Instantiate module with parameters"
+	${1:module_name} #(${2:parameters}) ${3:$1}_inst (${4:.*});
+snippet inv "Input vector"
+	input [${1:n}:${2:0}] ${3:input_name}_i
+snippet lpar "Local parameter"
+	localparam ${1:name} = ${0:value}
+snippet neg "Negative edge"
+	negedge ${0:signal}
+snippet out "Output"
+	output ${1:output_name}_o
+snippet outr "Output register"
+	output reg ${1:output_name}_o
+snippet outv "Output vector"
+	output [${1:n}:${2:0}] ${3:output_name}_o
+snippet outrv "Output register vector"
+	output reg [${1:n}:${2:0}] ${3:output_name}_o
+snippet par "Parameter definition"
+	parameter ${1:name} = ${0:value}
+snippet pos "Positive edge"
+	posedge ${0:signal}
+snippet r "Register variable"
+	reg ${1:reg_name};
+snippet rv "Register vector"
+	reg [${1:n}:${2:0}] ${3:reg_name};
+snippet rva "Register vector array"
+	reg [${1:n}:${2:0}] ${3:reg_name} [${4:0}:${5:m}];
+snippet v "Vector/array range"
+	[${1:n}:${2:0}]
+snippet w "Simple wire"
+	wire ${1:signal_name};
+snippet wv "Wire vector"
+	wire [${1:n}:${2:0}] ${3:signal_name};
+snippet if "if statement"
 	if (${1}) begin
-		${0}
+		${0:${VISUAL}}
 	end
-# If/else statements
-snippet ife
+snippet ife "If/else statements"
 	if (${1}) begin
-		${2}
+		${2:${VISUAL}}
 	end
 	else begin
-		${3}
+		${3:${VISUAL}}
 	end
-# Else if statement
-snippet eif
+snippet eif "Else if statement"
 	else if (${1}) begin
-		${0}
+		${0:${VISUAL}}
 	end
-#Else statement
-snippet el
+snippet el "Else statement"
 	else begin
-		${0}
+		${0:${VISUAL}}
 	end
-# While statement
-snippet wh
+snippet wh "While statement"
 	while (${1}) begin
-		${0}
+		${0:${VISUAL}}
 	end
-# Repeat Loop
-snippet rep
+snippet rep "Repeat Loop"
 	repeat (${1}) begin
-		${0}
+		${0:${VISUAL}}
 	end
-# Case statement
-snippet case
+snippet case "Case statement"
 	case (${1:/* variable */})
 		${2:/* value */}: begin
-			${3}
+			${3:${VISUAL}}
 		end
 		default: begin
-			${4}
+			${4:${VISUAL}}
 		end
 	endcase
-# CaseZ statement
-snippet casez
+snippet casez "CaseZ statement"
 	casez (${1:/* variable */})
 		${2:/* value */}: begin
-			${3}
+			${3:${VISUAL}}
 		end
 		default: begin
-			${4}
+			${4:${VISUAL}}
 		end
 	endcase
-# Always block
-snippet al
+snippet al "Always block"
 	always @(${1:/* sensitive list */}) begin
-		${0}
+		${2:${VISUAL}}
+	end
+snippet alc "Combinational always block"
+	always @* begin
+		${1:${VISUAL}}
+	end
+snippet alss "Sync sequential block"
+	always @(${1:posedge} ${2:clk}) begin
+		if (${3:rst}) begin
+			$4
+		end
+		else begin
+			$5
+		end
 	end
-# Module block
-snippet mod
+snippet alsa "Async sequential block"
+	always @(${1:posedge} ${2:clk}, ${3:posedge} ${4:rst}) begin
+		if ($4) begin
+			$5
+		end
+		else begin
+			$6
+		end
+	end
+snippet mod "Module block"
 	module ${1:`vim_snippets#Filename('$1', 'name')`} (${2});
-		${0}
+		${0:${VISUAL}}
+	endmodule
+snippet modp "Module with parameters"
+	module ${1:`vim_snippets#Filename('$1', 'name')`} #(${2}) (${3});
+		${0:${VISUAL}}
 	endmodule
-# For
-snippet for
-	for (int ${2:i} = 0; $2 < ${1:count}; $2${3:++}) begin
-		${4}
+snippet for "For"
+	for (${1:i} = ${2:0}; ${3:i < count}; ${4:i = i + 1}) begin
+		${5:${VISUAL}}
 	end
-# Forever
-snippet forev
+snippet forev "Forever"
 	forever begin
-		${0}
+		${0:${VISUAL}}
 	end
-# Function
-snippet fun
+snippet fun "Function"
 	function ${1:void} ${2:name}(${3});
-		${0}
+		${0:${VISUAL}}
 	endfunction: $2
-# Task
-snippet task
+snippet task "Task"
 	task ${1:name}(${2});
-		${0}
+		${0:${VISUAL}}
 	endtask: $1
-# Initial 
-snippet ini
+snippet ini "Initial "
 	initial begin
-		${0}
-	end
-# typedef struct packed
-snippet tdsp
-	typedef struct packed {
-		int ${2:data};
-	} ${1:`vim_snippets#Filename('$1_t', 'name')`};
-# typedef eum
-snippet tde
-	typedef enum ${2:logic[15:0]}
-	{
-		${3:REG = 16'h0000}
-	} ${1:my_dest_t};
+		${0:${VISUAL}}
+	end
diff --git a/snippets/verilog_systemverilog.snippets b/snippets/verilog_systemverilog.snippets
new file mode 100644
index 000000000..07d26b409
--- /dev/null
+++ b/snippets/verilog_systemverilog.snippets
@@ -0,0 +1 @@
+extends systemverilog