From 5134085ca6ae31e769b1fe7648f354c366a394e2 Mon Sep 17 00:00:00 2001 From: Jeremy Soller Date: Fri, 14 Mar 2025 15:13:20 -0600 Subject: [PATCH 1/4] Add darp11 and darp11-b --- src/mainboard/system76/mtl/Kconfig | 21 +- src/mainboard/system76/mtl/Kconfig.name | 6 + .../system76/mtl/variants/darp11/board.fmd | 13 ++ .../mtl/variants/darp11/board_info.txt | 2 + .../system76/mtl/variants/darp11/data.vbt | Bin 0 -> 7680 bytes .../system76/mtl/variants/darp11/gpio.c | 216 ++++++++++++++++++ .../system76/mtl/variants/darp11/gpio_early.c | 16 ++ .../system76/mtl/variants/darp11/hda_verb.c | 59 +++++ .../mtl/variants/darp11/overridetree.cb | 112 +++++++++ .../system76/mtl/variants/darp11/ramstage.c | 17 ++ .../system76/mtl/variants/darp11/romstage.c | 25 ++ 11 files changed, 486 insertions(+), 1 deletion(-) create mode 100644 src/mainboard/system76/mtl/variants/darp11/board.fmd create mode 100644 src/mainboard/system76/mtl/variants/darp11/board_info.txt create mode 100644 src/mainboard/system76/mtl/variants/darp11/data.vbt create mode 100644 src/mainboard/system76/mtl/variants/darp11/gpio.c create mode 100644 src/mainboard/system76/mtl/variants/darp11/gpio_early.c create mode 100644 src/mainboard/system76/mtl/variants/darp11/hda_verb.c create mode 100644 src/mainboard/system76/mtl/variants/darp11/overridetree.cb create mode 100644 src/mainboard/system76/mtl/variants/darp11/ramstage.c create mode 100644 src/mainboard/system76/mtl/variants/darp11/romstage.c diff --git a/src/mainboard/system76/mtl/Kconfig b/src/mainboard/system76/mtl/Kconfig index a0515d905c..034ec3f60a 100644 --- a/src/mainboard/system76/mtl/Kconfig +++ b/src/mainboard/system76/mtl/Kconfig @@ -40,6 +40,20 @@ config BOARD_SYSTEM76_DARP10_B select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES select SOC_INTEL_METEORLAKE_U_H +config BOARD_SYSTEM76_DARP11 + select BOARD_SYSTEM76_MTL_COMMON + select EC_SYSTEM76_EC_FAN2 + select MAINBOARD_USES_IFD_GBE_REGION + select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES + select SOC_INTEL_METEORLAKE_U_H + +config BOARD_SYSTEM76_DARP11_B + select BOARD_SYSTEM76_MTL_COMMON + select EC_SYSTEM76_EC_FAN2 + select MAINBOARD_USES_IFD_GBE_REGION + select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES + select SOC_INTEL_METEORLAKE_U_H + config BOARD_SYSTEM76_LEMP13 select BOARD_SYSTEM76_MTL_COMMON select DRIVERS_I2C_TAS5825M @@ -61,6 +75,7 @@ config MAINBOARD_DIR config VARIANT_DIR default "darp10" if BOARD_SYSTEM76_DARP10 || BOARD_SYSTEM76_DARP10_B + default "darp11" if BOARD_SYSTEM76_DARP11 || BOARD_SYSTEM76_DARP11_B default "lemp13" if BOARD_SYSTEM76_LEMP13 || BOARD_SYSTEM76_LEMP13_B config OVERRIDE_DEVICETREE @@ -69,16 +84,20 @@ config OVERRIDE_DEVICETREE config MAINBOARD_PART_NUMBER default "darp10" if BOARD_SYSTEM76_DARP10 default "darp10-b" if BOARD_SYSTEM76_DARP10_B + default "darp11" if BOARD_SYSTEM76_DARP11 + default "darp11-b" if BOARD_SYSTEM76_DARP11_B default "lemp13" if BOARD_SYSTEM76_LEMP13 default "lemp13-b" if BOARD_SYSTEM76_LEMP13_B config MAINBOARD_SMBIOS_PRODUCT_NAME - default "Darter Pro" if BOARD_SYSTEM76_DARP10 || BOARD_SYSTEM76_DARP10_B + default "Darter Pro" if BOARD_SYSTEM76_DARP10 || BOARD_SYSTEM76_DARP10_B || BOARD_SYSTEM76_DARP11 || BOARD_SYSTEM76_DARP11_B default "Lemur Pro" if BOARD_SYSTEM76_LEMP13 || BOARD_SYSTEM76_LEMP13_B config MAINBOARD_VERSION default "darp10" if BOARD_SYSTEM76_DARP10 default "darp10-b" if BOARD_SYSTEM76_DARP10_B + default "darp11" if BOARD_SYSTEM76_DARP11 + default "darp11-b" if BOARD_SYSTEM76_DARP11_B default "lemp13" if BOARD_SYSTEM76_LEMP13 default "lemp13-b" if BOARD_SYSTEM76_LEMP13_B diff --git a/src/mainboard/system76/mtl/Kconfig.name b/src/mainboard/system76/mtl/Kconfig.name index 299c834f82..b0e214e866 100644 --- a/src/mainboard/system76/mtl/Kconfig.name +++ b/src/mainboard/system76/mtl/Kconfig.name @@ -6,6 +6,12 @@ config BOARD_SYSTEM76_DARP10 config BOARD_SYSTEM76_DARP10_B bool "darp10-b" +config BOARD_SYSTEM76_DARP11 + bool "darp11" + +config BOARD_SYSTEM76_DARP11_B + bool "darp11-b" + config BOARD_SYSTEM76_LEMP13 bool "lemp13" diff --git a/src/mainboard/system76/mtl/variants/darp11/board.fmd b/src/mainboard/system76/mtl/variants/darp11/board.fmd new file mode 100644 index 0000000000..2b8860d67f --- /dev/null +++ b/src/mainboard/system76/mtl/variants/darp11/board.fmd @@ -0,0 +1,13 @@ +FLASH 32M { + SI_DESC 16K + SI_GBE 8K + SI_ME 8612K + SI_BIOS@16M 16M { + RW_MRC_CACHE 64K + SMMSTORE(PRESERVE) 256K + WP_RO { + FMAP 4K + COREBOOT(CBFS) + } + } +} diff --git a/src/mainboard/system76/mtl/variants/darp11/board_info.txt b/src/mainboard/system76/mtl/variants/darp11/board_info.txt new file mode 100644 index 0000000000..a2b32815ed --- /dev/null +++ b/src/mainboard/system76/mtl/variants/darp11/board_info.txt @@ -0,0 +1,2 @@ +Board name: darp11 +Release year: 2025 diff --git a/src/mainboard/system76/mtl/variants/darp11/data.vbt b/src/mainboard/system76/mtl/variants/darp11/data.vbt new file mode 100644 index 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DEEP, NF1), // ESPI_IO1_EC + PAD_CFG_NF(GPP_A02, UP_20K, DEEP, NF1), // ESPI_IO2_EC + PAD_CFG_NF(GPP_A03, UP_20K, DEEP, NF1), // ESPI_IO3_EC + PAD_CFG_NF(GPP_A04, UP_20K, DEEP, NF1), // ESPI_CS_EC# + PAD_CFG_NF(GPP_A05, UP_20K, DEEP, NF1), // ESPI_CLK_EC + PAD_CFG_NF(GPP_A06, NONE, DEEP, NF1), // ESPI_RESET_N + // GPP_A07 missing + // GPP_A08 missing + // GPP_A09 missing + // GPP_A10 missing + PAD_CFG_GPO(GPP_A11, 0, DEEP), // ADDS_CODE + PAD_CFG_GPI(GPP_A12, NONE, DEEP), // WLAN_WAKEUP# + PAD_CFG_TERM_GPO(GPP_A13, 1, UP_20K, PLTRST), // M2_SSD2_RST# + PAD_NC(GPP_A14, NONE), + PAD_NC(GPP_A15, NONE), // CPU_SWI# (test point) + PAD_CFG_NF(GPP_A16, UP_20K, DEEP, NF1), // ESPI_ALRT0# + PAD_NC(GPP_A17, NONE), // TP_ATTN#_A17 + PAD_NC(GPP_A18, NONE), + PAD_NC(GPP_A19, NONE), + PAD_NC(GPP_A20, NONE), + PAD_CFG_NF(GPP_A21, NATIVE, DEEP, NF1), // PMC_I2C_INT + + PAD_CFG_GPI_INT(GPP_B00, NONE, PLTRST, LEVEL), // TP_ATTN#_B00 + PAD_NC(GPP_B01, NONE), + PAD_NC(GPP_B02, NONE), + PAD_NC(GPP_B03, NONE), + PAD_CFG_GPO(GPP_B04, 0, DEEP), // NO REBOOT strap + PAD_CFG_GPO(GPP_B05, 0, DEEP), // CPU_KBCRST# (test point) + PAD_CFG_GPO(GPP_B06, 0, DEEP), // ROM_I2C_EN + PAD_NC(GPP_B07, NONE), + PAD_NC(GPP_B08, NONE), + PAD_NC(GPP_B09, NONE), + PAD_NC(GPP_B10, NONE), + PAD_CFG_NF(GPP_B11, NONE, DEEP, NF2), // HDMI_HPD + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), // SLP_S0# + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLTRST# + PAD_CFG_GPI(GPP_B14, NONE, DEEP), // Top swap override strap + PAD_CFG_GPI(GPP_B15, NONE, DEEP), // GPP_B15_USB2_OC0_N + PAD_NC(GPP_B16, NONE), + PAD_NC(GPP_B17, NONE), + PAD_CFG_GPO(GPP_B18, 1, DEEP), // PCH_BT_EN + PAD_CFG_GPO(GPP_B19, 1, DEEP), // WIFI_RF_EN + PAD_NC(GPP_B20, NONE), + PAD_CFG_GPO(GPP_B21, 0, PLTRST), // TCP_RETIMER_FORCE_PWR + PAD_NC(GPP_B22, NONE), + PAD_NC(GPP_B23, NONE), + + PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1), // SMB_CLK + PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1), // SMB_DATA + PAD_CFG_NF(GPP_C02, NONE, DEEP, NF1), // TLS confidentiality strap + PAD_CFG_NF(GPP_C03, UP_20K, DEEP, NF1), // SML0_CLK + PAD_CFG_NF(GPP_C04, UP_20K, DEEP, NF1), // SML0_DATA + PAD_CFG_NF(GPP_C05, UP_20K, DEEP, NF1), // eSPI disabled strap + PAD_CFG_NF(GPP_C06, UP_20K, DEEP, NF1), // PMC_I2C_SCL + PAD_CFG_NF(GPP_C07, UP_20K, DEEP, NF1), // PMC_I2C_SDA + PAD_NC(GPP_C08, NONE), + PAD_NC(GPP_C09, NONE), + PAD_NC(GPP_C10, NONE), + PAD_CFG_NF(GPP_C11, NONE, PWROK, NF1), // CPU_LAN_CLKREQ# + PAD_CFG_NF(GPP_C12, NONE, PWROK, NF1), // CPU_CARD_CLKREQ# + PAD_NC(GPP_C13, NONE), + // GPP_C14 missing + PAD_CFG_GPO(GPP_C15, 0, DEEP), // GPP_C15_STRAP + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), // TBT_LSX0_TXD + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), // TBT_LSX0_RXD + PAD_NC(GPP_C18, NONE), + PAD_NC(GPP_C19, NONE), + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF2), // HDMI_CTRLCLK + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF2), // HDMI_CTRLDATA + PAD_NC(GPP_C22, NONE), + PAD_NC(GPP_C23, NONE), + + PAD_CFG_GPO(GPP_D00, 1, DEEP), // SB_BLON + PAD_CFG_GPO(GPP_D01, 1, DEEP), // SSD2_PWR_EN + PAD_CFG_GPO(GPP_D02, 1, DEEP), // M2_SSD1_RST# + PAD_NC(GPP_D03, NONE), + PAD_NC(GPP_D04, NONE), + PAD_CFG_GPO(GPP_D05, 1, DEEP), // SSD1_PWR_EN + PAD_NC(GPP_D06, NONE), + PAD_NC(GPP_D07, NONE), + PAD_NC(GPP_D08, NONE), + PAD_NC(GPP_D09, NONE), + PAD_CFG_NF(GPP_D10, NONE, DEEP, NF1), // HDA_BITCLK + PAD_CFG_NF(GPP_D11, NATIVE, DEEP, NF1), // HDA_SYNC + PAD_CFG_NF(GPP_D12, NATIVE, DEEP, NF1), // HDA_SDOUT / ME_WE + PAD_CFG_NF(GPP_D13, NATIVE, DEEP, NF1), // HDA_SDI0 + PAD_NC(GPP_D14, NONE), + PAD_NC(GPP_D15, NONE), + PAD_CFG_GPO(GPP_D16, 0, DEEP), // GPIO_SPK_MUTE + PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), // HDA_RST# + PAD_NC(GPP_D18, NONE), + PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), // CPU_SSD1_CLKREQ# + PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), // CPU_SSD2_CLKREQ# + PAD_CFG_NF(GPP_D21, NONE, DEEP, NF2), // CPU_WLAN_CLKREQ# + PAD_CFG_NF(GPP_D22, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPP_D23, NATIVE, DEEP, NF1), + + PAD_NC(GPP_E00, NONE), + _PAD_CFG_STRUCT(GPP_E01, 0x40100100, 0x3000), // TPM_PIRQ# + PAD_CFG_GPI(GPP_E02, NONE, DEEP), // BOARD_ID4 + PAD_CFG_GPI(GPP_E03, NONE, DEEP), // CNVI_WAKE# + PAD_NC(GPP_E04, NONE), + PAD_NC(GPP_E05, NONE), + PAD_CFG_GPO(GPP_E06, 0, DEEP), // JTAG ODT disable strap + PAD_NC(GPP_E07, NONE), + PAD_NC(GPP_E08, NONE), + PAD_CFG_GPI(GPP_E09, NONE, DEEP), // GPP_E9_USB2_OC0_N + PAD_NC(GPP_E10, NONE), + PAD_CFG_GPI(GPP_E11, NONE, DEEP), // BOARD_ID6 + PAD_NC(GPP_E12, NONE), + PAD_NC(GPP_E13, NONE), + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), // EDP_HPD + PAD_NC(GPP_E15, NONE), + PAD_CFG_NF(GPP_E16, NONE, DEEP, NF2), // VRALERT# + PAD_CFG_GPO(GPP_E17, 0, DEEP), // BOARD_ID5 + // GPP_E18 missing + // GPP_E19 missing + // GPP_E20 missing + // GPP_E21 missing + PAD_CFG_GPO(GPP_E22, 0, DEEP), // DNX_FORCE_RELOAD + + PAD_CFG_NF(GPP_F00, NONE, DEEP, NF1), // CNVI_BRI_DT + PAD_CFG_NF(GPP_F01, UP_20K, DEEP, NF1), // CNVI_BRI_RSP + PAD_CFG_NF(GPP_F02, NONE, DEEP, NF1), // CNVI_RGI_DT + PAD_CFG_NF(GPP_F03, UP_20K, DEEP, NF1), // CNVI_RGI_RSP + PAD_CFG_NF(GPP_F04, NONE, DEEP, NF1), // CNVI_RST# + PAD_CFG_NF(GPP_F05, NONE, DEEP, NF3), // CNVI_CLKREQ + PAD_CFG_GPO(GPP_F06, 0, DEEP), // CNVI_GNSS_PA_BLANKING + PAD_NC(GPP_F07, NONE), + PAD_NC(GPP_F08, NONE), + PAD_CFG_GPI(GPP_F09, NONE, DEEP), // TPM_DET + PAD_NC(GPP_F10, NONE), + PAD_CFG_GPO(GPP_F11, 0, DEEP), // BOARD_ID3 + PAD_NC(GPP_F12, NONE), // I2C_SCL_CODEC + PAD_NC(GPP_F13, NONE), // I2C_SDA_CODEC + PAD_CFG_GPO(GPP_F14, 0, DEEP), // BOARD_ID1 + PAD_CFG_GPO(GPP_F15, 0, DEEP), // BOARD_ID2 + PAD_NC(GPP_F16, NONE), + PAD_NC(GPP_F17, NONE), + PAD_CFG_GPO(GPP_F18, 0, DEEP), // CPU_CCD_WP# + PAD_NC(GPP_F19, NONE), + PAD_CFG_GPO(GPP_F20, 0, DEEP), // SVID support strap + PAD_NC(GPP_F21, NONE), + PAD_NC(GPP_F22, NONE), + PAD_NC(GPP_F23, NONE), + + PAD_CFG_GPO(GPP_H00, 0, DEEP), // eSPI flash sharing mode strap + PAD_CFG_GPO(GPP_H01, 0, DEEP), // SPI flash descriptor recovery strap + PAD_NC(GPP_H02, NONE), + // GPP_H03 missing + PAD_CFG_GPO(GPP_H04, 0, DEEP), // CNVI_MFUART2_RXD + PAD_CFG_GPO(GPP_H05, 0, DEEP), // CNVI_MFUART2_TXD + PAD_CFG_NF(GPP_H06, NONE, DEEP, NF1), // I2C3_SDA (Pantone) + PAD_CFG_NF(GPP_H07, NONE, DEEP, NF1), // I2C3_SCL (Pantone) + // GPP_H08 (UART0_RXD) configured in bootblock + // GPP_H09 (UART0_TXD) configured in bootblock + PAD_CFG_GPO(GPP_H10, 0, DEEP), + PAD_CFG_GPO(GPP_H11, 0, DEEP), + PAD_CFG_GPO(GPP_H12, 0, DEEP), + PAD_NC(GPP_H13, NONE), + PAD_NC(GPP_H14, NONE), + PAD_NC(GPP_H15, NONE), + PAD_NC(GPP_H16, NONE), + PAD_NC(GPP_H17, NONE), + // GPP_H18 missing + PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1), // I2C_SDA_TP + PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1), // I2C_SCL_TP + PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1), // PCH_I2C_SDA + PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1), // PCH_I2C_SCL + + PAD_NC(GPP_S00, NONE), + PAD_NC(GPP_S01, NONE), + PAD_NC(GPP_S02, NONE), // DMIC_CLK_A1 + PAD_NC(GPP_S03, NONE), // DMIC_DATA_A1 + PAD_NC(GPP_S04, NONE), + PAD_NC(GPP_S05, NONE), + PAD_NC(GPP_S06, NONE), + PAD_NC(GPP_S07, NONE), + + PAD_CFG_NF(GPP_V00, NONE, DEEP, NF1), // PM_BATLOW# + PAD_CFG_NF(GPP_V01, NONE, DEEP, NF1), // AC_PRESENT + PAD_CFG_NF(GPP_V02, NONE, DEEP, NF1), // LAN_WAKEUP# + PAD_CFG_NF(GPP_V03, NONE, DEEP, NF1), // PWR_BTN# + PAD_CFG_NF(GPP_V04, NONE, DEEP, NF1), // SUSB#_PCH + PAD_CFG_NF(GPP_V05, UP_20K, DEEP, NF1), // SUSC#_PCH + PAD_CFG_NF(GPP_V06, NATIVE, DEEP, NF1), // SLP_A# + // GPP_V07 missing + PAD_CFG_NF(GPP_V08, UP_20K, DEEP, NF1), // SUS_CLK + PAD_CFG_NF(GPP_V09, NONE, DEEP, NF1), // SLP_WLAN# + PAD_NC(GPP_V10, NONE), + PAD_CFG_NF(GPP_V11, NONE, DEEP, NF1), // LANPHYPC + PAD_CFG_GPO(GPP_V12, 0, DEEP), // SLP_LAN# + // GPP_V13 missing + PAD_CFG_NF(GPP_V14, NONE, DEEP, NF1), // PCIE_WAKE# + // GPP_V15 missing + // GPP_V16 missing + // GPP_V17 missing + // GPP_V18 missing + // GPP_V19 missing + // GPP_V20 missing + // GPP_V21 missing + PAD_NC(GPP_V22, NONE), + PAD_NC(GPP_V23, NONE), +}; + +void mainboard_configure_gpios(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/system76/mtl/variants/darp11/gpio_early.c b/src/mainboard/system76/mtl/variants/darp11/gpio_early.c new file mode 100644 index 0000000000..f17db26f3e --- /dev/null +++ b/src/mainboard/system76/mtl/variants/darp11/gpio_early.c @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +static const struct pad_config early_gpio_table[] = { + PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1), // SMB_CLK + PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1), // SMB_DATA + PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1), // UART0_RX + PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1), // UART0_TX +}; + +void mainboard_configure_early_gpios(void) +{ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} diff --git a/src/mainboard/system76/mtl/variants/darp11/hda_verb.c b/src/mainboard/system76/mtl/variants/darp11/hda_verb.c new file mode 100644 index 0000000000..2915f4d9eb --- /dev/null +++ b/src/mainboard/system76/mtl/variants/darp11/hda_verb.c @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +const u32 cim_verb_data[] = { + /* Realtek, ALC245 */ + 0x10ec0245, /* Vendor ID */ + 0x1558a763, /* Subsystem ID */ + 40, /* Number of entries */ + //AZALIA_SUBVENDOR(0, 0x1558a763), + AZALIA_SUBVENDOR(0, 0x1558a743), + AZALIA_RESET(1), + AZALIA_PIN_CFG(0, 0x12, 0x90a60130), + AZALIA_PIN_CFG(0, 0x13, 0x40000000), + AZALIA_PIN_CFG(0, 0x14, 0x90170110), + AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x40789b2d), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x21, 0x04211020), + + 0x05b50006, 0x05b40011, 0x0205001a, 0x0204810b, + 0x0205004a, 0x02042010, 0x02050038, 0x02047909, + 0x05c50000, 0x05c43d82, 0x05c50000, 0x05c43d82, + 0x05350000, 0x0534201a, 0x05350000, 0x0534201a, + 0x0535001d, 0x05340800, 0x0535001e, 0x05340800, + 0x05350003, 0x05341ec4, 0x05350004, 0x05340000, + 0x05450000, 0x05442000, 0x0545001d, 0x05440800, + 0x0545001e, 0x05440800, 0x05450003, 0x05441ec4, + 0x05450004, 0x05440000, 0x05350000, 0x0534a01a, + 0x0205003c, 0x0204f175, 0x0205003c, 0x0204f135, + 0x02050040, 0x02048800, 0x05a50001, 0x05a4001f, + 0x02050010, 0x02040020, 0x02050010, 0x02040020, + 0x0205006b, 0x0204a390, 0x0205006b, 0x0204a390, + 0x0205006c, 0x02040c9e, 0x0205006d, 0x02040c00, + 0x00170500, 0x00170500, 0x05a50004, 0x05a40113, + 0x02050008, 0x02046a8c, 0x02050076, 0x0204f000, + 0x0205000e, 0x020465c0, 0x02050033, 0x02048580, + 0x02050069, 0x0204fda8, 0x02050068, 0x02040000, + 0x02050003, 0x02040002, 0x02050069, 0x02040000, + 0x02050068, 0x02040001, 0x0205002e, 0x0204290e, + 0x02236100, 0x02235100, 0x00920011, 0x00970610, + 0x00936000, 0x00935000, 0x0205000d, 0x0204a020, + 0x00220011, 0x00270610, 0x0023a046, 0x00239046, + 0x0173b000, 0x01770740, 0x05a50001, 0x05a4001f, + 0x05c5000f, 0x05c40003, 0x02050036, 0x020437d7, + 0x0143b000, 0x01470740, 0x02050010, 0x02040020, + 0x01470c02, 0x01470c02, + + // XXX: Duplicate last 2 u32s to keep in 4-dword blocks + 0x01470c02, 0x01470c02, +}; + +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/system76/mtl/variants/darp11/overridetree.cb b/src/mainboard/system76/mtl/variants/darp11/overridetree.cb new file mode 100644 index 0000000000..8baa5560b9 --- /dev/null +++ b/src/mainboard/system76/mtl/variants/darp11/overridetree.cb @@ -0,0 +1,112 @@ +# SPDX-License-Identifier: GPL-2.0-only + +chip soc/intel/meteorlake + device domain 0 on + subsystemid 0x1558 0xa743 inherit + + device ref tbt_pcie_rp0 on end + device ref tcss_xhci on + register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)" + register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC_SKIP)" + # TCP2 is used as HDMI + # TCP3 is not used + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""TBT Type-C"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + device ref tcss_usb3_port0 on end + end + chip drivers/usb/acpi + register "desc" = ""USB Type-C"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + device ref tcss_usb3_port1 on end + end + end + end + end + device ref tcss_dma0 on end + device ref xhci on + register "usb2_ports" = "{ + [0] = USB2_PORT_MID(OC_SKIP), /* J_AUD1 / AJ_USB3_1 */ + [1] = USB2_PORT_MID(OC_SKIP), /* J_TYPEC1 */ + [2] = USB2_PORT_MID(OC_SKIP), /* J_USB3_1 */ + [5] = USB2_PORT_MID(OC_SKIP), /* TBT */ + [6] = USB2_PORT_MID(OC_SKIP), /* Camera */ + [9] = USB2_PORT_MID(OC_SKIP), /* Bluetooth */ + }" + register "usb3_ports" = "{ + [0] = USB3_PORT_DEFAULT(OC_SKIP), /* J_AUD1 / AJ_USB3_1 */ + [1] = USB3_PORT_DEFAULT(OC_SKIP), /* J_USB3_1 */ + }" + end + device ref i2c0 on + # Touchpad I2C bus + register "serial_io_i2c_mode[PchSerialIoIndexI2C0]" = "PchSerialIoPci" + chip drivers/i2c/hid + register "generic.hid" = ""ELAN0412"" + register "generic.desc" = ""ELAN Touchpad"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_B00)" + register "generic.detect" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 15 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""FTCS1000"" + register "generic.desc" = ""FocalTech Touchpad"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_B00)" + register "generic.detect" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 38 on end + end + end + device ref pcie_rp5 on + # GLAN + register "pcie_rp[PCH_RP(5)]" = "{ + .clk_src = 2, + .clk_req = 2, + .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_SRC_UNUSED, + }" + register "pcie_clk_config_flag[2]" = "PCIE_CLK_FREE_RUNNING" + device pci 00.0 on end + end + device ref pcie_rp6 on + # Card Reader + register "pcie_rp[PCH_RP(6)]" = "{ + .clk_src = 3, + .clk_req = 3, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + end + device ref pcie_rp8 on + # WLAN + register "pcie_rp[PCH_RP(8)]" = "{ + .clk_src = 5, + .clk_req = 5, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + end + device ref pcie_rp10 on + # SSD2 + # XXX: Schematics show RP[13:16] used + register "pcie_rp[PCH_RP(10)]" = "{ + .clk_src = 8, + .clk_req = 8, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + end + device ref pcie_rp11 on + # SSD1 + # XXX: Schematics show RP[17:20] used + register "pcie_rp[PCH_RP(11)]" = "{ + .clk_src = 7, + .clk_req = 7, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + end + device ref hda on + subsystemid 0x1558 0xa763 + end + device ref gbe on end + end +end diff --git a/src/mainboard/system76/mtl/variants/darp11/ramstage.c b/src/mainboard/system76/mtl/variants/darp11/ramstage.c new file mode 100644 index 0000000000..63dfb35151 --- /dev/null +++ b/src/mainboard/system76/mtl/variants/darp11/ramstage.c @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +void mainboard_silicon_init_params(FSP_S_CONFIG *params) +{ + // Enable TCP1 USB-A conversion + // BIT 0:3 is mapping to PCH XHCI USB2 port + // BIT 4:5 is reserved + // BIT 6 is orientational + // BIT 7 is enable + params->EnableTcssCovTypeA[1] = 0x82; + + // XXX: Enabling C10 reporting causes system to constantly enter and + // exit opportunistic suspend when idle. + params->PchEspiHostC10ReportEnable = 0; +} diff --git a/src/mainboard/system76/mtl/variants/darp11/romstage.c b/src/mainboard/system76/mtl/variants/darp11/romstage.c new file mode 100644 index 0000000000..b047f523ac --- /dev/null +++ b/src/mainboard/system76/mtl/variants/darp11/romstage.c @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + const struct mb_cfg board_cfg = { + .type = MEM_TYPE_DDR5, + .ect = true, + }; + const struct mem_spd spd_info = { + .topo = MEM_TOPO_DIMM_MODULE, + .smbus = { + [0] = { .addr_dimm[0] = 0x50, }, + [1] = { .addr_dimm[0] = 0x52, }, + }, + }; + const bool half_populated = false; + + mupd->FspmConfig.DmiMaxLinkSpeed = 4; + mupd->FspmConfig.GpioOverride = 0; + + memcfg_init(mupd, &board_cfg, &spd_info, half_populated); +} From d4b3f7bea4e0ee159ef7ed44ae9ba7b48c4418bc Mon Sep 17 00:00:00 2001 From: Jeremy Soller Date: Mon, 17 Mar 2025 14:00:03 -0600 Subject: [PATCH 2/4] WIP: add arrowlake CPU ID --- src/include/cpu/intel/cpu_ids.h | 1 + src/soc/intel/common/block/cpu/mp_init.c | 1 + src/soc/intel/meteorlake/bootblock/report_platform.c | 1 + 3 files changed, 3 insertions(+) diff --git a/src/include/cpu/intel/cpu_ids.h b/src/include/cpu/intel/cpu_ids.h index ad66025d5f..56897655f8 100644 --- a/src/include/cpu/intel/cpu_ids.h +++ b/src/include/cpu/intel/cpu_ids.h @@ -82,6 +82,7 @@ #define CPUID_RAPTORLAKE_Q0 0xb06a3 #define CPUID_LUNARLAKE_A0_1 0xb06d0 #define CPUID_LUNARLAKE_A0_2 0xb06d1 +#define CPUID_ARROWLAKE_H_TODO 0xc0652 #define CPUID_PANTHERLAKE_A0 0xc06c0 #define CPUID_SNOWRIDGE_A0 0x80660 #define CPUID_SNOWRIDGE_A1 0x80661 diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c index 95e52d5d9c..b2c6595ef4 100644 --- a/src/soc/intel/common/block/cpu/mp_init.c +++ b/src/soc/intel/common/block/cpu/mp_init.c @@ -33,6 +33,7 @@ static struct device_operations cpu_dev_ops = { static const struct cpu_device_id cpu_table[] = { { X86_VENDOR_INTEL, CPUID_PANTHERLAKE_A0, CPUID_EXACT_MATCH_MASK }, + { X86_VENDOR_INTEL, CPUID_ARROWLAKE_H_TODO, CPUID_EXACT_MATCH_MASK }, { X86_VENDOR_INTEL, CPUID_LUNARLAKE_A0_1, CPUID_EXACT_MATCH_MASK }, { X86_VENDOR_INTEL, CPUID_LUNARLAKE_A0_2, CPUID_EXACT_MATCH_MASK }, { X86_VENDOR_INTEL, CPUID_METEORLAKE_A0_1, CPUID_EXACT_MATCH_MASK }, diff --git a/src/soc/intel/meteorlake/bootblock/report_platform.c b/src/soc/intel/meteorlake/bootblock/report_platform.c index 405698962d..b937179f70 100644 --- a/src/soc/intel/meteorlake/bootblock/report_platform.c +++ b/src/soc/intel/meteorlake/bootblock/report_platform.c @@ -22,6 +22,7 @@ static struct { { CPUID_METEORLAKE_A0_2, "MeteorLake A0" }, { CPUID_METEORLAKE_B0, "MeteorLake B0" }, { CPUID_METEORLAKE_C0, "MeteorLake C0" }, + { CPUID_ARROWLAKE_H_TODO, "ArrowLake-H TODO" }, }; static struct { From 90ca4c703ddaae8e5d7632e07ad0425e562ed609 Mon Sep 17 00:00:00 2001 From: Jeremy Soller Date: Tue, 18 Mar 2025 10:51:26 -0600 Subject: [PATCH 3/4] Add ArrowLake-H device ids from Intel doc 777369 --- src/drivers/intel/ish/ish.c | 1 + src/include/cpu/intel/cpu_ids.h | 2 +- src/include/device/pci_ids.h | 46 +++++++++++++++++++ src/soc/intel/common/block/cnvi/cnvi.c | 1 + src/soc/intel/common/block/cpu/mp_init.c | 2 +- src/soc/intel/common/block/cse/cse.c | 1 + src/soc/intel/common/block/dsp/dsp.c | 1 + .../intel/common/block/fast_spi/fast_spi.c | 1 + .../intel/common/block/graphics/graphics.c | 1 + src/soc/intel/common/block/hda/hda.c | 1 + src/soc/intel/common/block/i2c/i2c.c | 6 +++ src/soc/intel/common/block/lpc/lpc.c | 1 + src/soc/intel/common/block/p2sb/p2sb.c | 1 + src/soc/intel/common/block/pcie/pcie.c | 9 ++++ src/soc/intel/common/block/pmc/pmc.c | 1 + src/soc/intel/common/block/sata/sata.c | 1 + src/soc/intel/common/block/smbus/smbus.c | 1 + src/soc/intel/common/block/spi/spi.c | 3 ++ src/soc/intel/common/block/sram/sram.c | 1 + .../common/block/systemagent/systemagent.c | 1 + .../intel/common/block/tracehub/tracehub.c | 1 + src/soc/intel/common/block/uart/uart.c | 3 ++ src/soc/intel/common/block/xdci/xdci.c | 1 + src/soc/intel/common/block/xhci/xhci.c | 1 + .../meteorlake/bootblock/report_platform.c | 5 +- src/soc/intel/meteorlake/chip.h | 1 + 26 files changed, 91 insertions(+), 3 deletions(-) diff --git a/src/drivers/intel/ish/ish.c b/src/drivers/intel/ish/ish.c index d83af4699d..bd99053250 100644 --- a/src/drivers/intel/ish/ish.c +++ b/src/drivers/intel/ish/ish.c @@ -86,6 +86,7 @@ static const unsigned short pci_device_ids[] = { PCI_DID_INTEL_PTL_U_H_ISHB, PCI_DID_INTEL_LNL_ISHB, PCI_DID_INTEL_MTL_ISHB, + PCI_DID_INTEL_ARL_ISHB, PCI_DID_INTEL_CNL_ISHB, PCI_DID_INTEL_CML_ISHB, PCI_DID_INTEL_TGL_ISHB, diff --git a/src/include/cpu/intel/cpu_ids.h b/src/include/cpu/intel/cpu_ids.h index 56897655f8..38dd4bb8ce 100644 --- a/src/include/cpu/intel/cpu_ids.h +++ b/src/include/cpu/intel/cpu_ids.h @@ -82,7 +82,7 @@ #define CPUID_RAPTORLAKE_Q0 0xb06a3 #define CPUID_LUNARLAKE_A0_1 0xb06d0 #define CPUID_LUNARLAKE_A0_2 0xb06d1 -#define CPUID_ARROWLAKE_H_TODO 0xc0652 +#define CPUID_ARROWLAKE_H_A0 0xc0652 #define CPUID_PANTHERLAKE_A0 0xc06c0 #define CPUID_SNOWRIDGE_A0 0x80660 #define CPUID_SNOWRIDGE_A1 0x80661 diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 481bf20eef..9b97ed222c 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -2182,6 +2182,7 @@ #define PCI_DID_INTEL_TGL_ISHB 0xa0fc #define PCI_DID_INTEL_TGL_H_ISHB 0x43fc #define PCI_DID_INTEL_MTL_ISHB 0x7e45 +#define PCI_DID_INTEL_ARL_ISHB 0x7745 #define PCI_DID_INTEL_ADL_N_ISHB 0x54fc #define PCI_DID_INTEL_ADL_P_ISHB 0x51fc #define PCI_DID_INTEL_LNL_ISHB 0xa845 @@ -3128,6 +3129,7 @@ #define PCI_DID_INTEL_MTL_ESPI_5 0x7e05 #define PCI_DID_INTEL_MTL_ESPI_6 0x7e06 #define PCI_DID_INTEL_MTL_ESPI_7 0x7e07 +#define PCI_DID_INTEL_ARL_H_ESPI 0x7202 #define PCI_DID_INTEL_RPP_P_ESPI_0 0x5180 #define PCI_DID_INTEL_RPP_P_ADP_P_ESPI_1 0x5181 #define PCI_DID_INTEL_RPP_P_ADP_P_ESPI_2 0x5182 @@ -3591,6 +3593,16 @@ #define PCI_DID_INTEL_MTL_IOE_P_PCIE_RP11 0x7ecb #define PCI_DID_INTEL_MTL_IOE_P_PCIE_RP12 0x7ecc +#define PCI_DID_INTEL_ARL_SOC_PCIE_RP1 0x7738 +#define PCI_DID_INTEL_ARL_SOC_PCIE_RP2 0x7739 +#define PCI_DID_INTEL_ARL_SOC_PCIE_RP3 0x773a +#define PCI_DID_INTEL_ARL_SOC_PCIE_RP4 0x773b +#define PCI_DID_INTEL_ARL_SOC_PCIE_RP5 0x773c +#define PCI_DID_INTEL_ARL_SOC_PCIE_RP6 0x773d +#define PCI_DID_INTEL_ARL_SOC_PCIE_RP7 0x773e +#define PCI_DID_INTEL_ARL_SOC_PCIE_RP8 0x773f +#define PCI_DID_INTEL_ARL_SOC_PCIE_RP9 0x774d + #define PCI_DID_INTEL_RPL_P_PCIE_RP1 0xa74d #define PCI_DID_INTEL_RPL_P_PCIE_RP2 0xa70d #define PCI_DID_INTEL_RPL_P_PCIE_RP3 0xa72d @@ -3738,6 +3750,7 @@ #define PCI_DID_INTEL_ADP_M_SATA_2 0x54d7 #define PCI_DID_INTEL_ADP_M_SATA_3 0x282a #define PCI_DID_INTEL_MTL_SATA 0x7e63 +#define PCI_DID_INTEL_ARL_SATA 0x7763 #define PCI_DID_INTEL_RPP_P_SATA_1 0x51d3 #define PCI_DID_INTEL_RPP_P_SATA_2 0x51d7 #define PCI_DID_INTEL_RPP_S_SATA 0x7a62 @@ -3765,6 +3778,7 @@ #define PCI_DID_INTEL_MTL_SOC_PMC 0x7e21 #define PCI_DID_INTEL_MTL_IOE_M_PMC 0x7ebe #define PCI_DID_INTEL_MTL_IOE_P_PMC 0x7ece +#define PCI_DID_INTEL_ARL_SOC_PMC 0x7721 #define PCI_DID_INTEL_RPP_P_PMC 0x51a1 #define PCI_DID_INTEL_RPP_S_PMC 0x7a21 #define PCI_DID_INTEL_LNL_PMC 0xa821 @@ -3894,6 +3908,13 @@ #define PCI_DID_INTEL_MTL_I2C4 0x7e50 #define PCI_DID_INTEL_MTL_I2C5 0x7e51 +#define PCI_DID_INTEL_ARL_I2C0 0x7778 +#define PCI_DID_INTEL_ARL_I2C1 0x7779 +#define PCI_DID_INTEL_ARL_I2C2 0x777A +#define PCI_DID_INTEL_ARL_I2C3 0x777B +#define PCI_DID_INTEL_ARL_I2C4 0x7750 +#define PCI_DID_INTEL_ARL_I2C5 0x7751 + #define PCI_DID_INTEL_LNL_I2C0 0xa878 #define PCI_DID_INTEL_LNL_I2C1 0xa879 #define PCI_DID_INTEL_LNL_I2C2 0xa87a @@ -3993,6 +4014,10 @@ #define PCI_DID_INTEL_MTL_UART1 0x7e26 #define PCI_DID_INTEL_MTL_UART2 0x7e52 +#define PCI_DID_INTEL_ARL_UART0 0x7725 +#define PCI_DID_INTEL_ARL_UART1 0x7726 +#define PCI_DID_INTEL_ARL_UART2 0x7752 + #define PCI_DID_INTEL_LNL_UART0 0xa825 #define PCI_DID_INTEL_LNL_UART1 0xa826 #define PCI_DID_INTEL_LNL_UART2 0xa852 @@ -4098,6 +4123,11 @@ #define PCI_DID_INTEL_MTL_GSPI1 0x7e30 #define PCI_DID_INTEL_MTL_GSPI2 0x7e46 +#define PCI_DID_INTEL_ARL_HWSEQ_SPI 0x7723 +#define PCI_DID_INTEL_ARL_GSPI0 0x7727 +#define PCI_DID_INTEL_ARL_GSPI1 0x7730 +#define PCI_DID_INTEL_ARL_GSPI2 0x7746 + #define PCI_DID_INTEL_LNL_HWSEQ_SPI 0xa823 #define PCI_DID_INTEL_LNL_GSPI0 0xa827 #define PCI_DID_INTEL_LNL_GSPI1 0xa830 @@ -4256,6 +4286,7 @@ #define PCI_DID_INTEL_MTL_P_GT2_3 0x7d55 #define PCI_DID_INTEL_MTL_P_GT2_4 0x7d60 #define PCI_DID_INTEL_MTL_P_GT2_5 0x7dd5 +#define PCI_DID_INTEL_ARL_H_GT2 0x7d51 #define PCI_DID_INTEL_RPL_HX_GT1 0xa788 #define PCI_DID_INTEL_RPL_HX_GT2 0xa78b #define PCI_DID_INTEL_RPL_HX_GT3 0x4688 @@ -4400,6 +4431,7 @@ #define PCI_DID_INTEL_MTL_P_ID_3 0x7d14 #define PCI_DID_INTEL_MTL_P_ID_4 0x7d15 #define PCI_DID_INTEL_MTL_P_ID_5 0x7d16 +#define PCI_DID_INTEL_ARL_H_ID 0x7d20 #define PCI_DID_INTEL_RPL_HX_ID_1 0xa702 #define PCI_DID_INTEL_RPL_HX_ID_2 0xa729 #define PCI_DID_INTEL_RPL_HX_ID_3 0xa728 @@ -4453,6 +4485,7 @@ #define PCI_DID_INTEL_ADP_S_SMBUS 0x7aa3 #define PCI_DID_INTEL_ADP_M_N_SMBUS 0x54a3 #define PCI_DID_INTEL_MTL_SMBUS 0x7e22 +#define PCI_DID_INTEL_ARL_SMBUS 0x7722 #define PCI_DID_INTEL_RPP_P_SMBUS 0x51a3 #define PCI_DID_INTEL_RPP_S_SMBUS 0x7a23 #define PCI_DID_INTEL_LNL_SMBUS 0xa822 @@ -4496,6 +4529,7 @@ #define PCI_DID_INTEL_MTL_XHCI 0x7e7d #define PCI_DID_INTEL_MTL_M_TCSS_XHCI 0x7eb0 #define PCI_DID_INTEL_MTL_P_TCSS_XHCI 0x7ec0 +#define PCI_DID_INTEL_ARL_XHCI 0x777d #define PCI_DID_INTEL_RPP_P_TCSS_XHCI 0xa71e #define PCI_DID_INTEL_RPP_S_XHCI 0x7a60 #define PCI_DID_INTEL_LNL_XHCI 0xa87d @@ -4529,6 +4563,7 @@ #define PCI_DID_INTEL_MTL_SOC_P2SB 0x7e20 #define PCI_DID_INTEL_MTL_IOE_M_P2SB 0x7eb8 #define PCI_DID_INTEL_MTL_IOE_P_P2SB 0x7ec8 +#define PCI_DID_INTEL_ARL_SOC_P2SB 0x7720 #define PCI_DID_INTEL_RPP_P_P2SB 0x51a0 #define PCI_DID_INTEL_RPP_S_P2SB 0x7a20 #define PCI_DID_INTEL_LNL_P2SB 0xa820 @@ -4552,6 +4587,7 @@ #define PCI_DID_INTEL_MTL_SOC_SRAM 0x7e7f #define PCI_DID_INTEL_MTL_IOE_M_SRAM 0x7ebf #define PCI_DID_INTEL_MTL_IOE_P_SRAM 0x7ecf +#define PCI_DID_INTEL_ARL_SOC_SRAM 0x777f #define PCI_DID_INTEL_LNL_SRAM 0xa87f #define PCI_DID_INTEL_PTL_H_SRAM 0xe47f #define PCI_DID_INTEL_PTL_U_H_SRAM 0xe37f @@ -4612,6 +4648,8 @@ #define PCI_DID_INTEL_MTL_AUDIO_7 0x7e2e #define PCI_DID_INTEL_MTL_AUDIO_8 0x7e2f +#define PCI_DID_INTEL_ARL_AUDIO 0x7728 + #define PCI_DID_INTEL_LNL_AUDIO_1 0xa828 #define PCI_DID_INTEL_LNL_AUDIO_2 0xa829 #define PCI_DID_INTEL_LNL_AUDIO_3 0xa82a @@ -4682,6 +4720,7 @@ #define PCI_DID_INTEL_RPP_S_CSE2 0x7a6c #define PCI_DID_INTEL_RPP_S_CSE3 0x7a6d #define PCI_DID_INTEL_MTL_CSE0 0x7e70 +#define PCI_DID_INTEL_ARL_CSE0 0x7770 #define PCI_DID_INTEL_LNL_CSE0 0xa870 #define PCI_DID_INTEL_PTL_H_CSE0 0xe470 #define PCI_DID_INTEL_PTL_U_H_CSE0 0xe370 @@ -4708,6 +4747,7 @@ #define PCI_DID_INTEL_MTL_XDCI 0x7e7e #define PCI_DID_INTEL_MTL_M_TCSS_XDCI 0x7eb1 #define PCI_DID_INTEL_MTL_P_TCSS_XDCI 0x7ec1 +#define PCI_DID_INTEL_ARL_XDCI 0x777e #define PCI_DID_INTEL_PTL_H_XDCI 0xe47e #define PCI_DID_INTEL_PTL_U_H_XDCI 0xe37e @@ -4862,6 +4902,7 @@ #define PCI_DID_INTEL_MTL_CNVI_WIFI_1 0x7e41 #define PCI_DID_INTEL_MTL_CNVI_WIFI_2 0x7e42 #define PCI_DID_INTEL_MTL_CNVI_WIFI_3 0x7e43 +#define PCI_DID_INTEL_ARL_CNVI_WIFI 0x7740 #define PCI_DID_INTEL_RPL_S_CNVI_WIFI_0 0x7a70 #define PCI_DID_INTEL_RPL_S_CNVI_WIFI_1 0x7a71 #define PCI_DID_INTEL_RPL_S_CNVI_WIFI_2 0x7a72 @@ -4901,6 +4942,7 @@ /* Intel Trace Hub */ #define PCI_DID_INTEL_MTL_TRACEHUB 0x7e24 +#define PCI_DID_INTEL_ARL_TRACEHUB 0x7724 #define PCI_DID_INTEL_RPL_TRACEHUB 0xa76f #define PCI_DID_INTEL_PTL_H_TRACEHUB 0xe424 #define PCI_DID_INTEL_PTL_U_H_TRACEHUB 0xe324 @@ -4915,6 +4957,10 @@ #define PCI_DID_INTEL_MTL_THC0_2 0x7e49 #define PCI_DID_INTEL_MTL_THC1_1 0x7e4a #define PCI_DID_INTEL_MTL_THC1_2 0x7e4b +#define PCI_DID_INTEL_ARL_THC0_1 0x7748 +#define PCI_DID_INTEL_ARL_THC0_2 0x7749 +#define PCI_DID_INTEL_ARL_THC1_1 0x774a +#define PCI_DID_INTEL_ARL_THC1_2 0x774b #define PCI_VID_COMPUTONE 0x8e0e #define PCI_DID_COMPUTONE_IP2EX 0x0291 diff --git a/src/soc/intel/common/block/cnvi/cnvi.c b/src/soc/intel/common/block/cnvi/cnvi.c index 08a6d683c5..6f56a61641 100644 --- a/src/soc/intel/common/block/cnvi/cnvi.c +++ b/src/soc/intel/common/block/cnvi/cnvi.c @@ -37,6 +37,7 @@ static const unsigned short wifi_pci_device_ids[] = { PCI_DID_INTEL_MTL_CNVI_WIFI_1, PCI_DID_INTEL_MTL_CNVI_WIFI_2, PCI_DID_INTEL_MTL_CNVI_WIFI_3, + PCI_DID_INTEL_ARL_CNVI_WIFI, PCI_DID_INTEL_CML_LP_CNVI_WIFI, PCI_DID_INTEL_CML_H_CNVI_WIFI, PCI_DID_INTEL_CNL_LP_CNVI_WIFI, diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c index b2c6595ef4..3fd5232167 100644 --- a/src/soc/intel/common/block/cpu/mp_init.c +++ b/src/soc/intel/common/block/cpu/mp_init.c @@ -33,13 +33,13 @@ static struct device_operations cpu_dev_ops = { static const struct cpu_device_id cpu_table[] = { { X86_VENDOR_INTEL, CPUID_PANTHERLAKE_A0, CPUID_EXACT_MATCH_MASK }, - { X86_VENDOR_INTEL, CPUID_ARROWLAKE_H_TODO, CPUID_EXACT_MATCH_MASK }, { X86_VENDOR_INTEL, CPUID_LUNARLAKE_A0_1, CPUID_EXACT_MATCH_MASK }, { X86_VENDOR_INTEL, CPUID_LUNARLAKE_A0_2, CPUID_EXACT_MATCH_MASK }, { X86_VENDOR_INTEL, CPUID_METEORLAKE_A0_1, CPUID_EXACT_MATCH_MASK }, { X86_VENDOR_INTEL, CPUID_METEORLAKE_A0_2, CPUID_EXACT_MATCH_MASK }, { X86_VENDOR_INTEL, CPUID_METEORLAKE_B0, CPUID_EXACT_MATCH_MASK }, { X86_VENDOR_INTEL, CPUID_METEORLAKE_C0, CPUID_EXACT_MATCH_MASK }, + { X86_VENDOR_INTEL, CPUID_ARROWLAKE_H_A0, CPUID_EXACT_MATCH_MASK }, { X86_VENDOR_INTEL, CPUID_SKYLAKE_C0, CPUID_EXACT_MATCH_MASK }, { X86_VENDOR_INTEL, CPUID_SKYLAKE_D0, CPUID_EXACT_MATCH_MASK }, { X86_VENDOR_INTEL, CPUID_SKYLAKE_HQ0, CPUID_EXACT_MATCH_MASK }, diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index 80ce388a3e..41f7221856 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -1491,6 +1491,7 @@ static const unsigned short pci_device_ids[] = { PCI_DID_INTEL_PTL_U_H_CSE0, PCI_DID_INTEL_LNL_CSE0, PCI_DID_INTEL_MTL_CSE0, + PCI_DID_INTEL_ARL_CSE0, PCI_DID_INTEL_APL_CSE0, PCI_DID_INTEL_GLK_CSE0, PCI_DID_INTEL_CNL_CSE0, diff --git a/src/soc/intel/common/block/dsp/dsp.c b/src/soc/intel/common/block/dsp/dsp.c index ab0e1168a4..59593bc0c4 100644 --- a/src/soc/intel/common/block/dsp/dsp.c +++ b/src/soc/intel/common/block/dsp/dsp.c @@ -45,6 +45,7 @@ static const unsigned short pci_device_ids[] = { PCI_DID_INTEL_MTL_AUDIO_6, PCI_DID_INTEL_MTL_AUDIO_7, PCI_DID_INTEL_MTL_AUDIO_8, + PCI_DID_INTEL_ARL_AUDIO, PCI_DID_INTEL_RPP_P_AUDIO, PCI_DID_INTEL_RPP_S_AUDIO_1, PCI_DID_INTEL_RPP_S_AUDIO_2, diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c index 91eb1aa72c..1abaf737df 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi.c +++ b/src/soc/intel/common/block/fast_spi/fast_spi.c @@ -588,6 +588,7 @@ static const unsigned short pci_device_ids[] = { PCI_DID_INTEL_LWB_SPI_SUPER, PCI_DID_INTEL_MCC_SPI0, PCI_DID_INTEL_MTL_HWSEQ_SPI, + PCI_DID_INTEL_ARL_HWSEQ_SPI, PCI_DID_INTEL_RPP_S_HWSEQ_SPI, PCI_DID_INTEL_SPR_HWSEQ_SPI, PCI_DID_INTEL_TGP_SPI0, diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index f1e7d7e547..225a7da47e 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -363,6 +363,7 @@ static const unsigned short pci_device_ids[] = { PCI_DID_INTEL_MTL_P_GT2_3, PCI_DID_INTEL_MTL_P_GT2_4, PCI_DID_INTEL_MTL_P_GT2_5, + PCI_DID_INTEL_ARL_H_GT2, PCI_DID_INTEL_APL_IGD_HD_505, PCI_DID_INTEL_APL_IGD_HD_500, PCI_DID_INTEL_CNL_GT2_ULX_1, diff --git a/src/soc/intel/common/block/hda/hda.c b/src/soc/intel/common/block/hda/hda.c index 59ecb502af..7af1b251ad 100644 --- a/src/soc/intel/common/block/hda/hda.c +++ b/src/soc/intel/common/block/hda/hda.c @@ -53,6 +53,7 @@ static const unsigned short pci_device_ids[] = { PCI_DID_INTEL_MTL_AUDIO_6, PCI_DID_INTEL_MTL_AUDIO_7, PCI_DID_INTEL_MTL_AUDIO_8, + PCI_DID_INTEL_ARL_AUDIO, PCI_DID_INTEL_RPP_P_AUDIO, PCI_DID_INTEL_RPP_S_AUDIO_1, PCI_DID_INTEL_RPP_S_AUDIO_2, diff --git a/src/soc/intel/common/block/i2c/i2c.c b/src/soc/intel/common/block/i2c/i2c.c index 679d425a90..0c63dd8980 100644 --- a/src/soc/intel/common/block/i2c/i2c.c +++ b/src/soc/intel/common/block/i2c/i2c.c @@ -198,6 +198,12 @@ static const unsigned short pci_device_ids[] = { PCI_DID_INTEL_MTL_I2C3, PCI_DID_INTEL_MTL_I2C4, PCI_DID_INTEL_MTL_I2C5, + PCI_DID_INTEL_ARL_I2C0, + PCI_DID_INTEL_ARL_I2C1, + PCI_DID_INTEL_ARL_I2C2, + PCI_DID_INTEL_ARL_I2C3, + PCI_DID_INTEL_ARL_I2C4, + PCI_DID_INTEL_ARL_I2C5, PCI_DID_INTEL_APL_I2C0, PCI_DID_INTEL_APL_I2C1, PCI_DID_INTEL_APL_I2C2, diff --git a/src/soc/intel/common/block/lpc/lpc.c b/src/soc/intel/common/block/lpc/lpc.c index ef14914968..99f21ee5bc 100644 --- a/src/soc/intel/common/block/lpc/lpc.c +++ b/src/soc/intel/common/block/lpc/lpc.c @@ -221,6 +221,7 @@ static const unsigned short pci_device_ids[] = { PCI_DID_INTEL_MTL_ESPI_5, PCI_DID_INTEL_MTL_ESPI_6, PCI_DID_INTEL_MTL_ESPI_7, + PCI_DID_INTEL_ARL_H_ESPI, PCI_DID_INTEL_RPP_P_ESPI_0, PCI_DID_INTEL_RPP_P_ADP_P_ESPI_1, PCI_DID_INTEL_RPP_P_ADP_P_ESPI_2, diff --git a/src/soc/intel/common/block/p2sb/p2sb.c b/src/soc/intel/common/block/p2sb/p2sb.c index 27e969cb55..2bc3c70da5 100644 --- a/src/soc/intel/common/block/p2sb/p2sb.c +++ b/src/soc/intel/common/block/p2sb/p2sb.c @@ -141,6 +141,7 @@ static const unsigned short pci_device_ids[] = { PCI_DID_INTEL_PTL_U_H_P2SB, PCI_DID_INTEL_LNL_P2SB, PCI_DID_INTEL_MTL_SOC_P2SB, + PCI_DID_INTEL_ARL_SOC_P2SB, PCI_DID_INTEL_RPP_P_P2SB, PCI_DID_INTEL_APL_P2SB, PCI_DID_INTEL_GLK_P2SB, diff --git a/src/soc/intel/common/block/pcie/pcie.c b/src/soc/intel/common/block/pcie/pcie.c index ddea3b667b..677d2577af 100644 --- a/src/soc/intel/common/block/pcie/pcie.c +++ b/src/soc/intel/common/block/pcie/pcie.c @@ -112,6 +112,15 @@ static const unsigned short pcie_device_ids[] = { PCI_DID_INTEL_MTL_IOE_P_PCIE_RP10, PCI_DID_INTEL_MTL_IOE_P_PCIE_RP11, PCI_DID_INTEL_MTL_IOE_P_PCIE_RP12, + PCI_DID_INTEL_ARL_SOC_PCIE_RP1, + PCI_DID_INTEL_ARL_SOC_PCIE_RP2, + PCI_DID_INTEL_ARL_SOC_PCIE_RP3, + PCI_DID_INTEL_ARL_SOC_PCIE_RP4, + PCI_DID_INTEL_ARL_SOC_PCIE_RP5, + PCI_DID_INTEL_ARL_SOC_PCIE_RP6, + PCI_DID_INTEL_ARL_SOC_PCIE_RP7, + PCI_DID_INTEL_ARL_SOC_PCIE_RP8, + PCI_DID_INTEL_ARL_SOC_PCIE_RP9, PCI_DID_INTEL_LWB_PCIE_RP1, PCI_DID_INTEL_LWB_PCIE_RP2, PCI_DID_INTEL_LWB_PCIE_RP3, diff --git a/src/soc/intel/common/block/pmc/pmc.c b/src/soc/intel/common/block/pmc/pmc.c index ca1c4b02bb..57b00c1c60 100644 --- a/src/soc/intel/common/block/pmc/pmc.c +++ b/src/soc/intel/common/block/pmc/pmc.c @@ -117,6 +117,7 @@ static const unsigned short pci_device_ids[] = { PCI_DID_INTEL_MTL_SOC_PMC, PCI_DID_INTEL_MTL_IOE_M_PMC, PCI_DID_INTEL_MTL_IOE_P_PMC, + PCI_DID_INTEL_ARL_SOC_PMC, PCI_DID_INTEL_RPP_P_PMC, PCI_DID_INTEL_DNV_PMC, PCI_DID_INTEL_LWB_PMC, diff --git a/src/soc/intel/common/block/sata/sata.c b/src/soc/intel/common/block/sata/sata.c index 96b7390791..efd9080b06 100644 --- a/src/soc/intel/common/block/sata/sata.c +++ b/src/soc/intel/common/block/sata/sata.c @@ -35,6 +35,7 @@ struct device_operations sata_ops = { static const unsigned short pci_device_ids[] = { PCI_DID_INTEL_MTL_SATA, + PCI_DID_INTEL_ARL_SATA, PCI_DID_INTEL_RPP_P_SATA_1, PCI_DID_INTEL_RPP_P_SATA_2, PCI_DID_INTEL_RPP_S_SATA, diff --git a/src/soc/intel/common/block/smbus/smbus.c b/src/soc/intel/common/block/smbus/smbus.c index 37e0cd2305..62a44b470d 100644 --- a/src/soc/intel/common/block/smbus/smbus.c +++ b/src/soc/intel/common/block/smbus/smbus.c @@ -53,6 +53,7 @@ static const unsigned short pci_device_ids[] = { PCI_DID_INTEL_PTL_U_H_SMBUS, PCI_DID_INTEL_LNL_SMBUS, PCI_DID_INTEL_MTL_SMBUS, + PCI_DID_INTEL_ARL_SMBUS, PCI_DID_INTEL_RPP_P_SMBUS, PCI_DID_INTEL_RPP_S_SMBUS, PCI_DID_INTEL_APL_SMBUS, diff --git a/src/soc/intel/common/block/spi/spi.c b/src/soc/intel/common/block/spi/spi.c index 74f9e314cf..beac292c41 100644 --- a/src/soc/intel/common/block/spi/spi.c +++ b/src/soc/intel/common/block/spi/spi.c @@ -137,6 +137,9 @@ static const unsigned short pci_device_ids[] = { PCI_DID_INTEL_MTL_GSPI0, PCI_DID_INTEL_MTL_GSPI1, PCI_DID_INTEL_MTL_GSPI2, + PCI_DID_INTEL_ARL_GSPI0, + PCI_DID_INTEL_ARL_GSPI1, + PCI_DID_INTEL_ARL_GSPI2, PCI_DID_INTEL_APL_SPI0, PCI_DID_INTEL_APL_SPI1, PCI_DID_INTEL_APL_SPI2, diff --git a/src/soc/intel/common/block/sram/sram.c b/src/soc/intel/common/block/sram/sram.c index e63f8059eb..d7050ebc22 100644 --- a/src/soc/intel/common/block/sram/sram.c +++ b/src/soc/intel/common/block/sram/sram.c @@ -40,6 +40,7 @@ static const unsigned short pci_device_ids[] = { PCI_DID_INTEL_MTL_IOE_M_SRAM, PCI_DID_INTEL_MTL_IOE_P_SRAM, PCI_DID_INTEL_MTL_CRASHLOG_SRAM, + PCI_DID_INTEL_ARL_SOC_SRAM, PCI_DID_INTEL_APL_SRAM, PCI_DID_INTEL_GLK_SRAM, PCI_DID_INTEL_CMP_SRAM, diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index 5d9ac15fbc..025988e13e 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -424,6 +424,7 @@ static const unsigned short systemagent_ids[] = { PCI_DID_INTEL_MTL_P_ID_3, PCI_DID_INTEL_MTL_P_ID_4, PCI_DID_INTEL_MTL_P_ID_5, + PCI_DID_INTEL_ARL_H_ID, PCI_DID_INTEL_GLK_NB, PCI_DID_INTEL_APL_NB, PCI_DID_INTEL_CNL_ID_U, diff --git a/src/soc/intel/common/block/tracehub/tracehub.c b/src/soc/intel/common/block/tracehub/tracehub.c index ba56c4c6fc..c9f4228109 100644 --- a/src/soc/intel/common/block/tracehub/tracehub.c +++ b/src/soc/intel/common/block/tracehub/tracehub.c @@ -45,6 +45,7 @@ static const unsigned short pci_device_ids[] = { PCI_DID_INTEL_PTL_H_TRACEHUB, PCI_DID_INTEL_PTL_U_H_TRACEHUB, PCI_DID_INTEL_MTL_TRACEHUB, + PCI_DID_INTEL_ARL_TRACEHUB, PCI_DID_INTEL_RPL_TRACEHUB, 0 }; diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c index ef83f5342a..e42db4257a 100644 --- a/src/soc/intel/common/block/uart/uart.c +++ b/src/soc/intel/common/block/uart/uart.c @@ -369,6 +369,9 @@ static const unsigned short pci_device_ids[] = { PCI_DID_INTEL_MTL_UART0, PCI_DID_INTEL_MTL_UART1, PCI_DID_INTEL_MTL_UART2, + PCI_DID_INTEL_ARL_UART0, + PCI_DID_INTEL_ARL_UART1, + PCI_DID_INTEL_ARL_UART2, PCI_DID_INTEL_APL_UART0, PCI_DID_INTEL_APL_UART1, PCI_DID_INTEL_APL_UART2, diff --git a/src/soc/intel/common/block/xdci/xdci.c b/src/soc/intel/common/block/xdci/xdci.c index 86625da968..bd3917cae6 100644 --- a/src/soc/intel/common/block/xdci/xdci.c +++ b/src/soc/intel/common/block/xdci/xdci.c @@ -31,6 +31,7 @@ static const unsigned short pci_device_ids[] = { PCI_DID_INTEL_PTL_H_XDCI, PCI_DID_INTEL_PTL_U_H_XDCI, PCI_DID_INTEL_MTL_XDCI, + PCI_DID_INTEL_ARL_XDCI, PCI_DID_INTEL_APL_XDCI, PCI_DID_INTEL_CNL_LP_XDCI, PCI_DID_INTEL_GLK_XDCI, diff --git a/src/soc/intel/common/block/xhci/xhci.c b/src/soc/intel/common/block/xhci/xhci.c index 6d35f39afb..1cdf21f45c 100644 --- a/src/soc/intel/common/block/xhci/xhci.c +++ b/src/soc/intel/common/block/xhci/xhci.c @@ -135,6 +135,7 @@ static const unsigned short pci_device_ids[] = { PCI_DID_INTEL_PTL_U_H_XHCI, PCI_DID_INTEL_LNL_XHCI, PCI_DID_INTEL_MTL_XHCI, + PCI_DID_INTEL_ARL_XHCI, PCI_DID_INTEL_APL_XHCI, PCI_DID_INTEL_CNL_LP_XHCI, PCI_DID_INTEL_GLK_XHCI, diff --git a/src/soc/intel/meteorlake/bootblock/report_platform.c b/src/soc/intel/meteorlake/bootblock/report_platform.c index b937179f70..71455bb000 100644 --- a/src/soc/intel/meteorlake/bootblock/report_platform.c +++ b/src/soc/intel/meteorlake/bootblock/report_platform.c @@ -22,7 +22,7 @@ static struct { { CPUID_METEORLAKE_A0_2, "MeteorLake A0" }, { CPUID_METEORLAKE_B0, "MeteorLake B0" }, { CPUID_METEORLAKE_C0, "MeteorLake C0" }, - { CPUID_ARROWLAKE_H_TODO, "ArrowLake-H TODO" }, + { CPUID_ARROWLAKE_H_A0, "ArrowLake-H A0" }, }; static struct { @@ -35,6 +35,7 @@ static struct { { PCI_DID_INTEL_MTL_P_ID_3, "MeteorLake P" }, { PCI_DID_INTEL_MTL_P_ID_4, "MeteorLake P" }, { PCI_DID_INTEL_MTL_P_ID_5, "MeteorLake P" }, + { PCI_DID_INTEL_ARL_H_ID, "ArrowLake-H" }, }; static struct { @@ -49,6 +50,7 @@ static struct { { PCI_DID_INTEL_MTL_ESPI_5, "MeteorLake SOC" }, { PCI_DID_INTEL_MTL_ESPI_6, "MeteorLake SOC" }, { PCI_DID_INTEL_MTL_ESPI_7, "MeteorLake SOC" }, + { PCI_DID_INTEL_ARL_H_ESPI, "ArrowLake-H SOC" }, }; static struct { @@ -61,6 +63,7 @@ static struct { { PCI_DID_INTEL_MTL_P_GT2_3, "MeteorLake-P GT2" }, { PCI_DID_INTEL_MTL_P_GT2_4, "Meteorlake-P GT2" }, { PCI_DID_INTEL_MTL_P_GT2_5, "Meteorlake-P GT2" }, + { PCI_DID_INTEL_ARL_H_GT2, "ArrowLake-H GT2" }, }; static inline uint8_t get_dev_revision(pci_devfn_t dev) diff --git a/src/soc/intel/meteorlake/chip.h b/src/soc/intel/meteorlake/chip.h index 777e66030b..07ef08f928 100644 --- a/src/soc/intel/meteorlake/chip.h +++ b/src/soc/intel/meteorlake/chip.h @@ -65,6 +65,7 @@ static const struct { { PCI_DID_INTEL_MTL_P_ID_2, MTL_P_282_242_CORE, TDP_15W }, { PCI_DID_INTEL_MTL_P_ID_3, MTL_P_682_482_CORE, TDP_28W }, { PCI_DID_INTEL_MTL_P_ID_1, MTL_P_682_482_CORE, TDP_28W }, + { PCI_DID_INTEL_ARL_H_ID, MTL_P_682_482_CORE, TDP_28W }, }; /* Types of display ports */ From c6a687a137ceabb9397fc1310a29f9c494745f5e Mon Sep 17 00:00:00 2001 From: Jeremy Soller Date: Tue, 18 Mar 2025 12:12:09 -0600 Subject: [PATCH 4/4] Add another ArrowLake MCH ID --- src/include/device/pci_ids.h | 3 ++- src/soc/intel/common/block/systemagent/systemagent.c | 3 ++- src/soc/intel/meteorlake/bootblock/report_platform.c | 3 ++- src/soc/intel/meteorlake/chip.h | 3 ++- 4 files changed, 8 insertions(+), 4 deletions(-) diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 9b97ed222c..c6e8c1e764 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -4431,7 +4431,8 @@ #define PCI_DID_INTEL_MTL_P_ID_3 0x7d14 #define PCI_DID_INTEL_MTL_P_ID_4 0x7d15 #define PCI_DID_INTEL_MTL_P_ID_5 0x7d16 -#define PCI_DID_INTEL_ARL_H_ID 0x7d20 +#define PCI_DID_INTEL_ARL_H_ID_1 0x7d06 +#define PCI_DID_INTEL_ARL_H_ID_2 0x7d20 #define PCI_DID_INTEL_RPL_HX_ID_1 0xa702 #define PCI_DID_INTEL_RPL_HX_ID_2 0xa729 #define PCI_DID_INTEL_RPL_HX_ID_3 0xa728 diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index 025988e13e..80f1e9e638 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -424,7 +424,8 @@ static const unsigned short systemagent_ids[] = { PCI_DID_INTEL_MTL_P_ID_3, PCI_DID_INTEL_MTL_P_ID_4, PCI_DID_INTEL_MTL_P_ID_5, - PCI_DID_INTEL_ARL_H_ID, + PCI_DID_INTEL_ARL_H_ID_1, + PCI_DID_INTEL_ARL_H_ID_2, PCI_DID_INTEL_GLK_NB, PCI_DID_INTEL_APL_NB, PCI_DID_INTEL_CNL_ID_U, diff --git a/src/soc/intel/meteorlake/bootblock/report_platform.c b/src/soc/intel/meteorlake/bootblock/report_platform.c index 71455bb000..6e0ed96e7e 100644 --- a/src/soc/intel/meteorlake/bootblock/report_platform.c +++ b/src/soc/intel/meteorlake/bootblock/report_platform.c @@ -35,7 +35,8 @@ static struct { { PCI_DID_INTEL_MTL_P_ID_3, "MeteorLake P" }, { PCI_DID_INTEL_MTL_P_ID_4, "MeteorLake P" }, { PCI_DID_INTEL_MTL_P_ID_5, "MeteorLake P" }, - { PCI_DID_INTEL_ARL_H_ID, "ArrowLake-H" }, + { PCI_DID_INTEL_ARL_H_ID_1, "ArrowLake-H" }, + { PCI_DID_INTEL_ARL_H_ID_2, "ArrowLake-H" }, }; static struct { diff --git a/src/soc/intel/meteorlake/chip.h b/src/soc/intel/meteorlake/chip.h index 07ef08f928..32a90271c5 100644 --- a/src/soc/intel/meteorlake/chip.h +++ b/src/soc/intel/meteorlake/chip.h @@ -65,7 +65,8 @@ static const struct { { PCI_DID_INTEL_MTL_P_ID_2, MTL_P_282_242_CORE, TDP_15W }, { PCI_DID_INTEL_MTL_P_ID_3, MTL_P_682_482_CORE, TDP_28W }, { PCI_DID_INTEL_MTL_P_ID_1, MTL_P_682_482_CORE, TDP_28W }, - { PCI_DID_INTEL_ARL_H_ID, MTL_P_682_482_CORE, TDP_28W }, + { PCI_DID_INTEL_ARL_H_ID_1, MTL_P_682_482_CORE, TDP_28W }, + { PCI_DID_INTEL_ARL_H_ID_2, MTL_P_682_482_CORE, TDP_28W }, }; /* Types of display ports */