Use ECAM for reading PCIe config space

[crawfxrd]

Replace x86-specific port IO access with ECAM for reading PCIe config space.

firmware-update/src/app/pci.rs

Lines 109 to 115 in 2325f02

	let address = 0x80000000
	| (u32::from(bus) << 16)
	| (u32::from(dev) << 11)
	| (u32::from(func) << 8)
	| u32::from(offset);
	Pio::<u32>::new(0xCF8).write(address);
	Ok(Pio::<u32>::new(0xCFC).read())

[crawfxrd]

Since the goal is to work on AArch64, might be better to gate implementation per arch?

• x86_64: Continue using port IO
• aarch64: Parse devicetree to determine address

I've got not clue how that works though.

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We should still do PCIe access using ECAM. But other things like SuperIO and EC would be accessed through devicetree.