A chisel based riscv 5-stage pipelined cpu design, implementing 32-bit version of the ISA (incomplete).
verilatorv4.016 recommended by Chisel. Tested on v4.210.riscv-gnu-toolchainTo build the C program
Run this command is SBT shell
testOnly nucleusrv.components.TopTest -- -DwriteVcd=1 -DprogramFile=/path/to/instructions/hex- Clone
riscv-arch-testrepo in nucleusrv rootgit clone git@github.com:riscv-non-isa/riscv-arch-test.git -b 1.0 - Build the simulation executable as defined in "Building with SBT" section
- Run
./run-compliance.shin root directory
-
In
tools/testsdirectory, create a folder and write c program in themain.cfile -
Run
make PROGRAM=<your_newly_created_test_folder_name> inside tools directory -
Build the program with
sbtcommand listed above. Make sure you are in root directory -
Optionally, you can skip writing/building c program and directly write hex instructions to
program.hexfile intools/outdirectory.