Homework 1

hw1.t.v

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+`include "hw1.v"
+
+module demorgan_test ();
+
+  // Instantiate device/module under test
+  reg A, B;                // Primary test inputs
+  wire nA, nB, nAandnB;    // Test outputs
+
+  demorgan dut(A, B, nA, nB, nAandnB, n_AorB, nAornB, n_AandB);  // Module to be tested
+
+
+  // Run sequence of test stimuli
+  initial begin
+    $display("A B | ~A ~B | ~A~B | ~(A+B) | ~A+~B | ~(AB)");            // Prints header for truth table
+    A=0;B=0; #1                                 // Set A and B, wait for update (#1)
+    $display("%b %b |  %b  %b |    %b |      %b |     %b |     %b ", A,B, nA, nB, nAandnB, n_AorB, nAornB, n_AandB);
+    A=0;B=1; #1                                 // Set A and B, wait for new update
+    $display("%b %b |  %b  %b |    %b |      %b |     %b |     %b ", A,B, nA, nB, nAandnB, n_AorB, nAornB, n_AandB);
+    A=1;B=0; #1
+    $display("%b %b |  %b  %b |    %b |      %b |     %b |     %b ", A,B, nA, nB, nAandnB, n_AorB, nAornB, n_AandB);
+    A=1;B=1; #1
+    $display("%b %b |  %b  %b |    %b |      %b |     %b |     %b ", A,B, nA, nB, nAandnB, n_AorB, nAornB, n_AandB);
+  end
+endmodule    // End demorgan_test

hw1.v

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+module demorgan
+(
+  input  A,          // Single bit inputs
+  input  B,
+  output nA,         // Output intermediate complemented inputs
+  output nB,
+  output nAandnB,    // Single bit output, (~A)*(~B)
+  output n_AorB,     // Signle bit output, ~(A+B)
+  output nAornB,     // Signle bit output, (~A)+(~B)
+  output n_AandB     // Signle bit output, ~(A*B)
+);
+
+  wire nA;
+  wire nB;
+  wire AandB;
+  wire AorB;
+
+  not Ainv(nA, A);  	// Top inverter is named Ainv, takes signal A as input and produces signal nA
+  not Binv(nB, B);
+  and andgate(nAandnB, nA, nB); 	// AND gate produces nAandnB from nA and nB
+  and andgate2(AandB, A, B);
+  or orgate1(AorB, A, B);
+  or orgate2(nAornB, nA, nB);
+  not not_and(n_AandB, AandB);
+  not not_or(n_AorB, AorB);
+
+endmodule

results.txt.txt

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+A B | ~A ~B | ~A~B | ~(A+B) | ~A+~B | ~(AB)
+0 0 |  1  1 |    1 |      1 |     1 |     1 
+0 1 |  1  0 |    0 |      0 |     1 |     1 
+1 0 |  0  1 |    0 |      0 |     1 |     1 
+1 1 |  0  0 |    0 |      0 |     0 |     0