HW1 Submission

hw1.t.v

@@ -0,0 +1,55 @@
+`include "hw1.v"
+
+module demorgan_test ();
+
+    reg A, B;
+    wire nA, nB, nAandnB;
+
+    demorgan dut(A, B, nA, nB, nAandnB, AorB, nAorB, AandB, nAandB, nAornB);
+
+    initial begin
+        $display("~A~B");
+        $display("A B | ~A ~B | ~A~B ");
+        A=0;B=0; #1
+        $display("%b %b |  %b  %b |    %b  ", A, B, nA, nB, nAandnB);
+        A=0;B=1; #1
+        $display("%b %b |  %b  %b |    %b  ", A, B, nA, nB, nAandnB);
+        A=1;B=0; #1
+        $display("%b %b |  %b  %b |    %b  ", A, B, nA, nB, nAandnB);
+        A=1;B=1; #1
+        $display("%b %b |  %b  %b |    %b  ", A, B, nA, nB, nAandnB);
+
+        $display("~(A+B)");
+        $display("A B | A+B | ~(A+B) ");
+        A=0;B=0; #1
+        $display("%b %b |  %b  |    %b  ", A, B, AorB, nAorB);
+        A=0;B=1; #1
+        $display("%b %b |  %b  |    %b  ", A, B, AorB, nAorB);
+        A=1;B=0; #1
+        $display("%b %b |  %b  |    %b  ", A, B, AorB, nAorB);
+        A=1;B=1; #1
+        $display("%b %b |  %b  |    %b  ", A, B, AorB, nAorB);
+
+        $display("~(AB)");
+        $display("A B | AB | ~(AB) ");
+        A=0;B=0; #1
+        $display("%b %b |  %b |   %b  ", A, B, AandB, nAandB);
+        A=0;B=1; #1
+        $display("%b %b |  %b |   %b  ", A, B, AandB, nAandB);
+        A=1;B=0; #1
+        $display("%b %b |  %b |   %b  ", A, B, AandB, nAandB);
+        A=1;B=1; #1
+        $display("%b %b |  %b |   %b  ", A, B, AandB, nAandB);
+
+        $display("(~A)+(~B)");
+        $display("A B | ~A ~B | (~A)+(~B) ");
+        A=0;B=0; #1
+        $display("%b %b |  %b  %b |    %b  ", A, B, nA, nB, nAornB);
+        A=0;B=1; #1
+        $display("%b %b |  %b  %b |    %b  ", A, B, nA, nB, nAornB);
+        A=1;B=0; #1
+        $display("%b %b |  %b  %b |    %b  ", A, B, nA, nB, nAornB);
+        A=1;B=1; #1
+        $display("%b %b |  %b  %b |    %b  ", A, B, nA, nB, nAornB);
+    end
+endmodule

hw1.v

@@ -0,0 +1,41 @@
+module demorgan
+(
+    input A,
+    input B,
+    output nA,
+    output nB,
+    output nAandnB,
+
+    //~(A+B)
+    output AorB,
+    output nAorB,
+
+    //~(AB)
+    output AandB,
+    output nAandB,
+
+    //(~A)+(~B)
+    output nAornB
+);
+
+    wire nA;
+    wire nB;
+    not Ainv(nA, A);
+    not Binv(nB, B);
+    and andgate(nAandnB, nA, nB);
+
+    //~(A+B)
+    wire AorB;
+    wire nAorB;
+    or orgate(AorB, A, B);
+    not AorBinv(nAorB, AorB);
+
+    //~(AB)
+    wire AandB;
+    wire nAandB;
+    and AandBgate(AandB, A, B);
+    not AandBinv(nAandB, AandB);
+
+    //(~A)+(~B)
+    or nAornBgate(nAornB, nA, nB);
+endmodule

results.txt

@@ -0,0 +1,24 @@
+~A~B
+A B | ~A ~B | ~A~B 
+0 0 |  1  1 |    1  
+0 1 |  1  0 |    0  
+1 0 |  0  1 |    0  
+1 1 |  0  0 |    0  
+~(A+B)
+A B | A+B | ~(A+B) 
+0 0 |  0  |    1  
+0 1 |  1  |    0  
+1 0 |  1  |    0  
+1 1 |  1  |    0  
+~(AB)
+A B | AB | ~(AB) 
+0 0 |  0 |   1  
+0 1 |  0 |   1  
+1 0 |  0 |   1  
+1 1 |  1 |   0  
+(~A)+(~B)
+A B | ~A ~B | (~A)+(~B) 
+0 0 |  1  1 |    1  
+0 1 |  1  0 |    1  
+1 0 |  0  1 |    1  
+1 1 |  0  0 |    0