Finished HW2

hw2.t.v

@@ -0,0 +1,90 @@
+`include "hw2.v"
+
+module fourtoonemux_test ();
+
+  // Instantiate device/module under test
+  reg A, B, C, D, Pick0, Pick1;                // Primary test inputs
+  wire Out;    // Test outputs
+
+  fourtoonemux mux(.A (A),.B (B),.C (C),.D (D),.Pick0 (Pick0),.Pick1 (Pick1),.Out (Out));  // Module to be tested
+
+
+  // Run sequence of test stimuli
+  initial begin
+    $display("A B C D Pick0 Pick1 | Out ");            // Prints header for truth table
+    A=0;B=0;C=0;D=0;Pick0=0;Pick1=0; #1000                                 // Set A and B, wait for update (#1)
+    $display("%b %b %b %b %b %b | %b", A,B,C,D,Pick0,Pick1,Out);
+    A=1;B=0;C=0;D=0;Pick0=0;Pick1=0; #1000                                 // Set A and B, wait for update (#1)
+    $display("%b %b %b %b %b %b | %b", A,B,C,D,Pick0,Pick1,Out);
+    A=0;B=0;C=0;D=0;Pick0=0;Pick1=0; #1000                                 // Set A and B, wait for update (#1)
+    $display("%b %b %b %b %b %b | %b", A,B,C,D,Pick0,Pick1,Out);
+    A=0;B=0;C=0;D=0;Pick0=1;Pick1=0; #1000                                 // Set A and B, wait for update (#1)
+    $display("%b %b %b %b %b %b | %b", A,B,C,D,Pick0,Pick1,Out);
+    A=0;B=1;C=0;D=0;Pick0=1;Pick1=0; #1000                                 // Set A and B, wait for update (#1)
+    $display("%b %b %b %b %b %b | %b", A,B,C,D,Pick0,Pick1,Out);
+    A=0;B=1;C=0;D=0;Pick0=1;Pick1=0; #1000                                 // Set A and B, wait for update (#1)
+    $display("%b %b %b %b %b %b | %b", A,B,C,D,Pick0,Pick1,Out);
+    A=0;B=1;C=1;D=0;Pick0=1;Pick1=0; #1000                                 // Set A and B, wait for update (#1)
+    $display("%b %b %b %b %b %b | %b", A,B,C,D,Pick0,Pick1,Out);
+    A=0;B=1;C=1;D=0;Pick0=1;Pick1=1; #1000                                 // Set A and B, wait for update (#1)
+    $display("%b %b %b %b %b %b | %b", A,B,C,D,Pick0,Pick1,Out);
+    A=0;B=1;C=1;D=1;Pick0=1;Pick1=1; #1000                                 // Set A and B, wait for update (#1)
+    $display("%b %b %b %b %b %b | %b", A,B,C,D,Pick0,Pick1,Out);
+  end
+endmodule    // End demorgan_test
+
+module fulladder_test ();
+
+  reg A,B,Cin;
+  wire O,Cout;
+
+  fulladder adder(.A (A),.B (B),.Cin (Cin),.O (O), .Cout (Cout));
+
+  initial begin
+    $display("A B Cin | O Cout");
+    A=0;B=0;Cin=0; #1000
+    $display("%b %b %b | %b %b", A,B,Cin,O,Cout);
+    A=0;B=0;Cin=1; #1000
+    $display("%b %b %b | %b %b", A,B,Cin,O,Cout);
+    A=0;B=1;Cin=0; #1000
+    $display("%b %b %b | %b %b", A,B,Cin,O,Cout);
+    A=0;B=1;Cin=1; #1000
+    $display("%b %b %b | %b %b", A,B,Cin,O,Cout);
+    A=1;B=0;Cin=0; #1000
+    $display("%b %b %b | %b %b", A,B,Cin,O,Cout);
+    A=1;B=0;Cin=1; #1000
+    $display("%b %b %b | %b %b", A,B,Cin,O,Cout);
+    A=1;B=1;Cin=0; #1000
+    $display("%b %b %b | %b %b", A,B,Cin,O,Cout);
+    A=1;B=1;Cin=1; #1000
+    $display("%b %b %b | %b %b", A,B,Cin,O,Cout);
+  end
+endmodule
+
+module decoder_test ();
+
+  reg A,B,En;
+  wire O0,O1,O2,O3;
+
+  decoder twoindecoder(.A (A),.B (B),.En (En),.O0 (O0),.O1 (O1),.O2 (O2),.O3 (O3));
+
+  initial begin
+    $display("A B En | Out3 Out2 Out1 Out0");
+    A=0;B=0;En=0; #1000
+    $display("%b %b %b | %b %b %b %b", A,B,En,O3,O2,O1,O0);
+    A=0;B=0;En=1; #1000
+    $display("%b %b %b | %b %b %b %b", A,B,En,O3,O2,O1,O0);
+    A=0;B=1;En=0; #1000
+    $display("%b %b %b | %b %b %b %b", A,B,En,O3,O2,O1,O0);
+    A=0;B=1;En=1; #1000
+    $display("%b %b %b | %b %b %b %b", A,B,En,O3,O2,O1,O0);
+    A=1;B=0;En=0; #1000
+    $display("%b %b %b | %b %b %b %b", A,B,En,O3,O2,O1,O0);
+    A=1;B=0;En=1; #1000
+    $display("%b %b %b | %b %b %b %b", A,B,En,O3,O2,O1,O0);
+    A=1;B=1;En=0; #1000
+    $display("%b %b %b | %b %b %b %b", A,B,En,O3,O2,O1,O0);
+    A=1;B=1;En=1; #1000
+    $display("%b %b %b | %b %b %b %b", A,B,En,O3,O2,O1,O0);
+  end
+endmodule

hw2.v

@@ -0,0 +1,80 @@
+`define AND and #50
+`define OR or #50
+`define NOT not #50
+`define XNOR xnor #50
+`define XOR xor #50
+
+module fourtoonemux(A,B,C,D,Pick0,Pick1,Out);
+
+  input A;
+  input B;
+  input C;
+  input D;
+  input Pick0;
+  input Pick1;
+  output Out;
+
+  wire nPick0;
+  wire nPick1;
+  wire isA;
+  wire isB;
+  wire isC;
+  wire isD;
+  wire Out;
+
+  `NOT Pick0inv(nPick0, Pick0);
+  `NOT Pick1inv(nPick1, Pick1);
+  `AND andA(isA, nPick0, nPick1, A);
+  `AND andB(isB, Pick0, nPick1, B);
+  `AND andC(isC, nPick0, Pick1, C);
+  `AND andD(isD, Pick0, Pick1, D);
+  `OR orgate(Out, isA, isB, isC, isD);
+
+endmodule
+
+module fulladder(A,B,Cin,O,Cout);
+
+  input A;
+  input B;
+  input Cin;
+  output O;
+  output Cout;
+
+  wire AxorB;
+  wire AxnorB;
+  wire AandB;
+  wire CinandAxorB;
+  wire nCin;
+  wire nCinandAxorB;
+  wire CinandAxnorB;
+
+  `XOR ABxor(AxorB, A, B);
+  `AND CinAxorBand(CinandAxorB, AxorB, Cin);
+  `AND AB(AandB, A, B);
+  `OR Carryout(Cout, AandB, CinandAxorB);
+  `NOT invCin(nCin, Cin);
+  `NOT nAxorB(AxnorB,AxorB);
+  `AND CinAxnorB(CinandAxnorB, AxnorB, Cin);
+  `AND nCinAxorB(nCinandAxorB, AxorB, nCin);
+  `OR orout(O, CinandAxnorB, nCinandAxorB);
+
+endmodule
+
+module decoder(A, B, En, O0, O1, O2, O3);
+
+  input A;
+  input B;
+  input En;
+  output O0;
+  output O1;
+  output O2;
+  output O3;
+
+  `NOT notA(nA, A);
+  `NOT notB(nB, B);
+  `AND out0(O0, nA, nB, En);
+  `AND out1(O1, nA, B, En);
+  `AND out2(O2, A, nB, En);
+  `AND out3(O3, A, B, En);
+
+endmodule