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HW Submission #4

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HW Submission #4

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Sep 17, 2017
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turning in HW
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turning in writeup
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Sep 20, 2017
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23 changes: 21 additions & 2 deletions adder.t.v
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Original file line number Diff line number Diff line change
Expand Up @@ -6,9 +6,28 @@ module testFullAdder();
reg a, b, carryin;
wire sum, carryout;

behavioralFullAdder adder (sum, carryout, a, b, carryin);
//behavioralFullAdder adder (sum, carryout, a, b, carryin);
structuralFullAdder adder (sum, carryout, a, b, carryin);

initial begin
// Your test code here
$dumpfile("adder.vcd");
$dumpvars(0, a, b, carryin, sum, carryout);
$display("A B Cin | Sum Cout | Expected Output");
a=0;b=0;carryin=0; #1000
$display("%b %b %b | %b %b | 0 0", a, b, carryin, sum, carryout);
a=0;b=0;carryin=1; #1000
$display("%b %b %b | %b %b | 1 0", a, b, carryin, sum, carryout);
a=0;b=1;carryin=0; #1000
$display("%b %b %b | %b %b | 1 0", a, b, carryin, sum, carryout);
a=0;b=1;carryin=1; #1000
$display("%b %b %b | %b %b | 0 1", a, b, carryin, sum, carryout);
a=1;b=0;carryin=0; #1000
$display("%b %b %b | %b %b | 1 0", a, b, carryin, sum, carryout);
a=1;b=0;carryin=1; #1000
$display("%b %b %b | %b %b | 0 1", a, b, carryin, sum, carryout);
a=1;b=1;carryin=0; #1000
$display("%b %b %b | %b %b | 0 1", a, b, carryin, sum, carryout);
a=1;b=1;carryin=1; #1000
$display("%b %b %b | %b %b | 1 1", a, b, carryin, sum, carryout);
end
endmodule
14 changes: 13 additions & 1 deletion adder.v
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Original file line number Diff line number Diff line change
@@ -1,4 +1,8 @@
// Adder circuit
`define AND and #50
`define OR or #50
`define NOT not #50
`define XOR xor #50

module behavioralFullAdder
(
Expand All @@ -20,5 +24,13 @@ module structuralFullAdder
input b,
input carryin
);
// Your adder code here
wire AxorB;
wire CAxorB;
wire AB;
`XOR(AxorB, a, b);
`XOR(sum, AxorB, carryin);
`AND(AB, a, b);
`AND(CAxorB, carryin, AxorB);
`OR(carryout, AB, CAxorB);

endmodule
40 changes: 21 additions & 19 deletions decoder.t.v
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Expand Up @@ -7,27 +7,29 @@ module testDecoder ();
reg enable;
wire out0,out1,out2,out3;

behavioralDecoder decoder (out0,out1,out2,out3,addr0,addr1,enable);
//structuralDecoder decoder (out0,out1,out2,out3,addr0,addr1,enable); // Swap after testing
//behavioralDecoder decoder (out0,out1,out2,out3,addr0,addr1,enable);
structuralDecoder decoder (out0,out1,out2,out3,addr0,addr1,enable); // Swap after testing

initial begin
$display("En A0 A1| O0 O1 O2 O3 | Expected Output");
enable=0;addr0=0;addr1=0; #1000
$display("%b %b %b | %b %b %b %b | All false", enable, addr0, addr1, out0, out1, out2, out3);
enable=0;addr0=1;addr1=0; #1000
$display("%b %b %b | %b %b %b %b | All false", enable, addr0, addr1, out0, out1, out2, out3);
enable=0;addr0=0;addr1=1; #1000
$display("%b %b %b | %b %b %b %b | All false", enable, addr0, addr1, out0, out1, out2, out3);
enable=0;addr0=1;addr1=1; #1000
$display("%b %b %b | %b %b %b %b | All false", enable, addr0, addr1, out0, out1, out2, out3);
enable=1;addr0=0;addr1=0; #1000
$display("%b %b %b | %b %b %b %b | O0 Only", enable, addr0, addr1, out0, out1, out2, out3);
enable=1;addr0=1;addr1=0; #1000
$display("%b %b %b | %b %b %b %b | O1 Only", enable, addr0, addr1, out0, out1, out2, out3);
enable=1;addr0=0;addr1=1; #1000
$display("%b %b %b | %b %b %b %b | O2 Only", enable, addr0, addr1, out0, out1, out2, out3);
enable=1;addr0=1;addr1=1; #1000
$display("%b %b %b | %b %b %b %b | O3 Only", enable, addr0, addr1, out0, out1, out2, out3);
$dumpfile("decoder.vcd");
$dumpvars(0, addr0, addr1, out0, out1, out2, out3, enable);
$display("En A0 A1| O0 O1 O2 O3 | Expected Output");
enable=0;addr0=0;addr1=0; #1000
$display("%b %b %b | %b %b %b %b | All false", enable, addr0, addr1, out0, out1, out2, out3);
enable=0;addr0=1;addr1=0; #1000
$display("%b %b %b | %b %b %b %b | All false", enable, addr0, addr1, out0, out1, out2, out3);
enable=0;addr0=0;addr1=1; #1000
$display("%b %b %b | %b %b %b %b | All false", enable, addr0, addr1, out0, out1, out2, out3);
enable=0;addr0=1;addr1=1; #1000
$display("%b %b %b | %b %b %b %b | All false", enable, addr0, addr1, out0, out1, out2, out3);
enable=1;addr0=0;addr1=0; #1000
$display("%b %b %b | %b %b %b %b | O0 Only", enable, addr0, addr1, out0, out1, out2, out3);
enable=1;addr0=1;addr1=0; #1000
$display("%b %b %b | %b %b %b %b | O1 Only", enable, addr0, addr1, out0, out1, out2, out3);
enable=1;addr0=0;addr1=1; #1000
$display("%b %b %b | %b %b %b %b | O2 Only", enable, addr0, addr1, out0, out1, out2, out3);
enable=1;addr0=1;addr1=1; #1000
$display("%b %b %b | %b %b %b %b | O3 Only", enable, addr0, addr1, out0, out1, out2, out3);
end

endmodule
26 changes: 22 additions & 4 deletions decoder.v
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Original file line number Diff line number Diff line change
@@ -1,4 +1,8 @@
// Decoder circuit
`define AND and #50
`define OR or #50
`define NOT not #50
`define XOR xor #50

module behavioralDecoder
(
Expand All @@ -14,9 +18,23 @@ endmodule
module structuralDecoder
(
output out0, out1, out2, out3,
input address0, address1,
input A, B,
input enable
);
// Your decoder code here
endmodule

wire nA;
wire nB;
wire AB;
wire nAB;
wire AnB;
wire nAnB;
`NOT(nA, A);
`NOT(nB, B);
`AND(nAnB, nA, nB);
`AND(AnB, A, nB);
`AND(nAB, nA, B);
`AND(AB, A, B);
`AND(out0, enable, nAnB);
`AND(out1, enable, AnB);
`AND(out2, enable, nAB);
`AND(out3, enable, AB);
endmodule
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22 changes: 21 additions & 1 deletion multiplexer.t.v
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Expand Up @@ -3,5 +3,25 @@
`include "multiplexer.v"

module testMultiplexer ();
// Your test code here
reg in0, in1, in2, in3;
reg addr0, addr1;
wire out;

//behavioralMultiplexer mux(out, addr0, addr1, in0, in1, in2, in3);
structuralMultiplexer mux(in0, in1, in2, in3, addr0, addr1, out);

initial begin
$dumpfile("multiplexer.vcd");
$dumpvars(0, in0, in1, in2, in3, addr0, addr1, out);
$display("A0 A 1| in0 in1 in2 in3 | Out | Expected Output");
in0=1;in1=0;in2=0;in3=0;addr0=0;addr1=0; #1000
$display("%b %b | %b %b %b %b | %b | O1 Only", addr0, addr1, in0, in1, in2, in3, out);
in0=0;in1=1;in2=0;in3=0;addr0=1;addr1=0; #1000
$display("%b %b | %b %b %b %b | %b | O2 Only", addr0, addr1, in0, in1, in2, in3, out);
in0=0;in1=0;in2=1;in3=0;addr0=0;addr1=1; #1000
$display("%b %b | %b %b %b %b | %b | O3 Only", addr0, addr1, in0, in1, in2, in3, out);
in0=0;in1=0;in2=0;in3=1;addr0=1;addr1=1; #1000
$display("%b %b | %b %b %b %b | %b | O4 Only", addr0, addr1, in0, in1, in2, in3, out);
end

endmodule
31 changes: 27 additions & 4 deletions multiplexer.v
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Expand Up @@ -15,10 +15,33 @@ endmodule

module structuralMultiplexer
(
output out,
input address0, address1,
input in0, in1, in2, in3
input in0, in1, in2, in3,
input A, B,
output out
);
// Your multiplexer code here
wire nA;
wire nB;
wire AB;
wire nAB;
wire AnB;
wire nAnB;
wire or1;
wire or2;
wire o0, o1, o2, o3;
not(nA, A);
not(nB, B);
and(nAnB, nA, nB);
and(AnB, A, nB);
and(nAB, nA, B);
and(AB, A, B);
and(o0, in0, nAnB);
and(o1, in1, AnB);
and(o2, in2, nAB);
and(o3, in3, AB);

or(or1, o0, o1);
or(or2, o2, o3);
or(out, or1, or2);

endmodule