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6fe6e18
Homework 2
mjakus Sep 22, 2017
eb19f0b
Added writeup, edited files
mjakus Sep 22, 2017
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153 changes: 153 additions & 0 deletions adder
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#! /usr/bin/vvp
:ivl_version "0.9.7 " "(v0_9_7)";
:vpi_time_precision - 12;
:vpi_module "system";
:vpi_module "v2005_math";
:vpi_module "va_math";
S_0xa42730 .scope module, "testFullAdder" "testFullAdder" 2 5;
.timescale -9 -12;
v0xa9ee70_0 .net "Cout", 0 0, L_0xaa0040; 1 drivers
v0xa9ef20_0 .var "a", 0 0;
v0xa9efa0_0 .var "b", 0 0;
v0xa9f070_0 .var "carryin", 0 0;
v0xa9f140_0 .net "carryout", 0 0, L_0xa9f2c0; 1 drivers
v0xa9f1c0_0 .net "structsum", 0 0, L_0xa9fdd0; 1 drivers
v0xa9f240_0 .net "sum", 0 0, L_0xa9f3b0; 1 drivers
S_0xa9e480 .scope module, "adder" "behavioralFullAdder" 2 10, 3 10, S_0xa42730;
.timescale -9 -12;
v0xa9e570_0 .net *"_s10", 0 0, C4<0>; 1 drivers
v0xa9e630_0 .net *"_s11", 1 0, L_0xa9f7b0; 1 drivers
v0xa9e6d0_0 .net *"_s13", 1 0, L_0xa9f9c0; 1 drivers
v0xa9e770_0 .net *"_s16", 0 0, C4<0>; 1 drivers
v0xa9e7f0_0 .net *"_s17", 1 0, L_0xa9fb30; 1 drivers
v0xa9e890_0 .net *"_s3", 1 0, L_0xa9f4f0; 1 drivers
v0xa9e930_0 .net *"_s6", 0 0, C4<0>; 1 drivers
v0xa9e9d0_0 .net *"_s7", 1 0, L_0xa9f620; 1 drivers
v0xa9eac0_0 .net "a", 0 0, v0xa9ef20_0; 1 drivers
v0xa9eb40_0 .net "b", 0 0, v0xa9efa0_0; 1 drivers
v0xa9ec50_0 .net "carryin", 0 0, v0xa9f070_0; 1 drivers
v0xa9ed00_0 .alias "carryout", 0 0, v0xa9f140_0;
v0xa9edf0_0 .alias "sum", 0 0, v0xa9f240_0;
L_0xa9f2c0 .part L_0xa9fb30, 1, 1;
L_0xa9f3b0 .part L_0xa9fb30, 0, 1;
L_0xa9f4f0 .concat [ 1 1 0 0], v0xa9ef20_0, C4<0>;
L_0xa9f620 .concat [ 1 1 0 0], v0xa9efa0_0, C4<0>;
L_0xa9f7b0 .arith/sum 2, L_0xa9f4f0, L_0xa9f620;
L_0xa9f9c0 .concat [ 1 1 0 0], v0xa9f070_0, C4<0>;
L_0xa9fb30 .arith/sum 2, L_0xa9f7b0, L_0xa9f9c0;
S_0xa42820 .scope module, "structural" "structuralFullAdder" 2 12, 3 22, S_0xa42730;
.timescale -9 -12;
L_0xa9ebc0/d .functor XOR 1, v0xa9ef20_0, v0xa9efa0_0, C4<0>, C4<0>;
L_0xa9ebc0 .delay (50000,50000,50000) L_0xa9ebc0/d;
L_0xa9fdd0/d .functor XOR 1, L_0xa9ebc0, v0xa9f070_0, C4<0>, C4<0>;
L_0xa9fdd0 .delay (50000,50000,50000) L_0xa9fdd0/d;
L_0xa9ff00/d .functor AND 1, v0xa9ef20_0, v0xa9efa0_0, C4<1>, C4<1>;
L_0xa9ff00 .delay (50000,50000,50000) L_0xa9ff00/d;
L_0xa9ffa0/d .functor AND 1, v0xa9f070_0, L_0xa9ebc0, C4<1>, C4<1>;
L_0xa9ffa0 .delay (50000,50000,50000) L_0xa9ffa0/d;
L_0xaa0040/d .functor OR 1, L_0xa9ff00, L_0xa9ffa0, C4<0>, C4<0>;
L_0xaa0040 .delay (50000,50000,50000) L_0xaa0040/d;
v0xa71af0_0 .net "AandB", 0 0, L_0xa9ff00; 1 drivers
v0xa9df80_0 .net "AxorB", 0 0, L_0xa9ebc0; 1 drivers
v0xa9e020_0 .net "CAxorB", 0 0, L_0xa9ffa0; 1 drivers
v0xa9e0c0_0 .alias "Cout", 0 0, v0xa9ee70_0;
v0xa9e170_0 .alias "a", 0 0, v0xa9eac0_0;
v0xa9e210_0 .alias "b", 0 0, v0xa9eb40_0;
v0xa9e2f0_0 .alias "carryin", 0 0, v0xa9ec50_0;
v0xa9e390_0 .alias "structsum", 0 0, v0xa9f1c0_0;
.scope S_0xa42730;
T_0 ;
%vpi_call 2 16 "$dumpfile", "adder.vcd";
%vpi_call 2 17 "$dumpvars";
%vpi_call 2 19 "$display", "Behavioral Full Adder";
%vpi_call 2 20 "$display", "A B CarryIn| Sum CarryOut | ExpectedSum ExpectedCarryOut";
%set/v v0xa9ef20_0, 0, 1;
%set/v v0xa9efa0_0, 0, 1;
%set/v v0xa9f070_0, 0, 1;
%delay 1000000, 0;
%vpi_call 2 22 "$display", "%b %b %b | %b %b | 0 0", v0xa9ef20_0, v0xa9efa0_0, v0xa9f070_0, v0xa9f240_0, v0xa9f140_0;
%set/v v0xa9ef20_0, 0, 1;
%set/v v0xa9efa0_0, 0, 1;
%set/v v0xa9f070_0, 1, 1;
%delay 1000000, 0;
%vpi_call 2 24 "$display", "%b %b %b | %b %b | 1 0", v0xa9ef20_0, v0xa9efa0_0, v0xa9f070_0, v0xa9f240_0, v0xa9f140_0;
%set/v v0xa9ef20_0, 0, 1;
%set/v v0xa9efa0_0, 1, 1;
%set/v v0xa9f070_0, 0, 1;
%delay 1000000, 0;
%vpi_call 2 26 "$display", "%b %b %b | %b %b | 1 0", v0xa9ef20_0, v0xa9efa0_0, v0xa9f070_0, v0xa9f240_0, v0xa9f140_0;
%set/v v0xa9ef20_0, 0, 1;
%set/v v0xa9efa0_0, 1, 1;
%set/v v0xa9f070_0, 1, 1;
%delay 1000000, 0;
%vpi_call 2 28 "$display", "%b %b %b | %b %b | 0 1", v0xa9ef20_0, v0xa9efa0_0, v0xa9f070_0, v0xa9f240_0, v0xa9f140_0;
%set/v v0xa9ef20_0, 1, 1;
%set/v v0xa9efa0_0, 0, 1;
%set/v v0xa9f070_0, 0, 1;
%delay 1000000, 0;
%vpi_call 2 30 "$display", "%b %b %b | %b %b | 1 0", v0xa9ef20_0, v0xa9efa0_0, v0xa9f070_0, v0xa9f240_0, v0xa9f140_0;
%set/v v0xa9ef20_0, 1, 1;
%set/v v0xa9efa0_0, 0, 1;
%set/v v0xa9f070_0, 1, 1;
%delay 1000000, 0;
%vpi_call 2 32 "$display", "%b %b %b | %b %b | 0 1", v0xa9ef20_0, v0xa9efa0_0, v0xa9f070_0, v0xa9f240_0, v0xa9f140_0;
%set/v v0xa9ef20_0, 1, 1;
%set/v v0xa9efa0_0, 1, 1;
%set/v v0xa9f070_0, 0, 1;
%delay 1000000, 0;
%vpi_call 2 34 "$display", "%b %b %b | %b %b | 0 1", v0xa9ef20_0, v0xa9efa0_0, v0xa9f070_0, v0xa9f240_0, v0xa9f140_0;
%set/v v0xa9ef20_0, 1, 1;
%set/v v0xa9efa0_0, 1, 1;
%set/v v0xa9f070_0, 1, 1;
%delay 1000000, 0;
%vpi_call 2 36 "$display", "%b %b %b | %b %b | 1 1", v0xa9ef20_0, v0xa9efa0_0, v0xa9f070_0, v0xa9f240_0, v0xa9f140_0;
%vpi_call 2 38 "$display", "Structural Full Adder";
%vpi_call 2 39 "$display", "A B CarryIn| Sum CarryOut | ExpectedSum ExpectedCarryOut";
%set/v v0xa9ef20_0, 0, 1;
%set/v v0xa9efa0_0, 0, 1;
%set/v v0xa9f070_0, 0, 1;
%delay 1000000, 0;
%vpi_call 2 41 "$display", "%b %b %b | %b %b | 0 0", v0xa9ef20_0, v0xa9efa0_0, v0xa9f070_0, v0xa9f1c0_0, v0xa9ee70_0;
%set/v v0xa9ef20_0, 0, 1;
%set/v v0xa9efa0_0, 0, 1;
%set/v v0xa9f070_0, 1, 1;
%delay 1000000, 0;
%vpi_call 2 43 "$display", "%b %b %b | %b %b | 1 0", v0xa9ef20_0, v0xa9efa0_0, v0xa9f070_0, v0xa9f1c0_0, v0xa9ee70_0;
%set/v v0xa9ef20_0, 0, 1;
%set/v v0xa9efa0_0, 1, 1;
%set/v v0xa9f070_0, 0, 1;
%delay 1000000, 0;
%vpi_call 2 45 "$display", "%b %b %b | %b %b | 1 0", v0xa9ef20_0, v0xa9efa0_0, v0xa9f070_0, v0xa9f1c0_0, v0xa9ee70_0;
%set/v v0xa9ef20_0, 0, 1;
%set/v v0xa9efa0_0, 1, 1;
%set/v v0xa9f070_0, 1, 1;
%delay 1000000, 0;
%vpi_call 2 47 "$display", "%b %b %b | %b %b | 0 1", v0xa9ef20_0, v0xa9efa0_0, v0xa9f070_0, v0xa9f1c0_0, v0xa9ee70_0;
%set/v v0xa9ef20_0, 1, 1;
%set/v v0xa9efa0_0, 0, 1;
%set/v v0xa9f070_0, 0, 1;
%delay 1000000, 0;
%vpi_call 2 49 "$display", "%b %b %b | %b %b | 1 0", v0xa9ef20_0, v0xa9efa0_0, v0xa9f070_0, v0xa9f1c0_0, v0xa9ee70_0;
%set/v v0xa9ef20_0, 1, 1;
%set/v v0xa9efa0_0, 0, 1;
%set/v v0xa9f070_0, 1, 1;
%delay 1000000, 0;
%vpi_call 2 51 "$display", "%b %b %b | %b %b | 0 1", v0xa9ef20_0, v0xa9efa0_0, v0xa9f070_0, v0xa9f1c0_0, v0xa9ee70_0;
%set/v v0xa9ef20_0, 1, 1;
%set/v v0xa9efa0_0, 1, 1;
%set/v v0xa9f070_0, 0, 1;
%delay 1000000, 0;
%vpi_call 2 53 "$display", "%b %b %b | %b %b | 0 1", v0xa9ef20_0, v0xa9efa0_0, v0xa9f070_0, v0xa9f1c0_0, v0xa9ee70_0;
%set/v v0xa9ef20_0, 1, 1;
%set/v v0xa9efa0_0, 1, 1;
%set/v v0xa9f070_0, 1, 1;
%delay 1000000, 0;
%vpi_call 2 55 "$display", "%b %b %b | %b %b | 1 1", v0xa9ef20_0, v0xa9efa0_0, v0xa9f070_0, v0xa9f1c0_0, v0xa9ee70_0;
%end;
.thread T_0;
# The file index is used to find the file name in the following table.
:file_names 4;
"N/A";
"<interactive>";
"adder.t.v";
"./adder.v";
72 changes: 58 additions & 14 deletions adder.t.v
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// Adder testbench
`timescale 1 ns / 1 ps
`include "adder.v"

module testFullAdder();
reg a, b, carryin;
wire sum, carryout;

behavioralFullAdder adder (sum, carryout, a, b, carryin);

initial begin
// Your test code here
end
endmodule
// Adder testbench
`timescale 1 ns / 1 ps
`include "adder.v"

module testFullAdder();
reg a, b, carryin;
wire sum, carryout;
wire structsum, AxorB, AandB, CAxorB, Cout;

behavioralFullAdder adder (sum, carryout, a, b, carryin);

structuralFullAdder structural(a, b, carryin, structsum, Cout);

initial begin

$dumpfile("adder.vcd");
$dumpvars();

$display("Behavioral Full Adder");
$display("A B CarryIn| Sum CarryOut | ExpectedSum ExpectedCarryOut");
a=0; b = 0; carryin = 0; #1000
$display("%b %b %b | %b %b | 0 0", a, b, carryin, sum, carryout);
a=0; b = 0; carryin = 1; #1000
$display("%b %b %b | %b %b | 1 0", a, b, carryin, sum, carryout);
a=0; b = 1; carryin = 0; #1000
$display("%b %b %b | %b %b | 1 0", a, b, carryin, sum, carryout);
a=0; b = 1; carryin = 1; #1000
$display("%b %b %b | %b %b | 0 1", a, b, carryin, sum, carryout);
a=1; b = 0; carryin = 0; #1000
$display("%b %b %b | %b %b | 1 0", a, b, carryin, sum, carryout);
a=1; b = 0; carryin = 1; #1000
$display("%b %b %b | %b %b | 0 1", a, b, carryin, sum, carryout);
a=1; b = 1; carryin = 0; #1000
$display("%b %b %b | %b %b | 0 1", a, b, carryin, sum, carryout);
a=1; b = 1; carryin = 1; #1000
$display("%b %b %b | %b %b | 1 1", a, b, carryin, sum, carryout);

$display("Structural Full Adder");
$display("A B CarryIn| Sum CarryOut | ExpectedSum ExpectedCarryOut");
a=0; b = 0; carryin = 0; #1000
$display("%b %b %b | %b %b | 0 0", a, b, carryin, structsum, Cout);
a=0; b = 0; carryin = 1; #1000
$display("%b %b %b | %b %b | 1 0", a, b, carryin, structsum, Cout);
a=0; b = 1; carryin = 0; #1000
$display("%b %b %b | %b %b | 1 0", a, b, carryin, structsum, Cout);
a=0; b = 1; carryin = 1; #1000
$display("%b %b %b | %b %b | 0 1", a, b, carryin, structsum, Cout);
a=1; b = 0; carryin = 0; #1000
$display("%b %b %b | %b %b | 1 0", a, b, carryin, structsum, Cout);
a=1; b = 0; carryin = 1; #1000
$display("%b %b %b | %b %b | 0 1", a, b, carryin, structsum, Cout);
a=1; b = 1; carryin = 0; #1000
$display("%b %b %b | %b %b | 0 1", a, b, carryin, structsum, Cout);
a=1; b = 1; carryin = 1; #1000
$display("%b %b %b | %b %b | 1 1", a, b, carryin, structsum, Cout);

end
endmodule
65 changes: 41 additions & 24 deletions adder.v
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@@ -1,24 +1,41 @@
// Adder circuit

module behavioralFullAdder
(
output sum,
output carryout,
input a,
input b,
input carryin
);
// Uses concatenation operator and built-in '+'
assign {carryout, sum}=a+b+carryin;
endmodule

module structuralFullAdder
(
output sum,
output carryout,
input a,
input b,
input carryin
);
// Your adder code here
endmodule
// Adder circuit
// an adder is a type of snake!

// Multiplexer circuit
`define AND and #50
`define OR or #50
`define NOT not #50
`define XOR xor #50

module behavioralFullAdder
(
output sum,
output carryout,
input a,
input b,
input carryin
);
// Uses concatenation operator and built-in '+'
assign {carryout, sum}=a+b+carryin;
endmodule

module structuralFullAdder
(
input a,
input b,
input carryin,
output structsum, Cout
);

wire AxorB;
wire AandB;
wire CAxorB;

`XOR xorgate1(AxorB, a, b);
`XOR xorgate2(structsum, AxorB, carryin);

`AND andgate1(AandB, a, b);
`AND andgate2(CAxorB, carryin, AxorB);
`OR orgate1(Cout, AandB, CAxorB);

endmodule
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