Submission of HW4

README.md

@@ -1,6 +1,7 @@
 # CompArch HW b0100: Register File #
 
 **Due:** ~~Monday, October 16~~ Thursday, October 19
+**_Please see report.md for deliverables 1 and 6 and testing_guide.md for instructions on how to run the tests_**
 
 This homework is intended to introduce behavioral Verilog and practice test bench design. You will create your first memory, a register file, which will be reused in your CPU design.
 

decoders.t.v

@@ -0,0 +1,41 @@
+//-------------------------------
+// Unit test the decoder module
+//-------------------------------
+
+`include "decoders.v"
+
+module decoder1to32Test();
+	wire[31:0] out;
+	reg enable;
+	reg[4:0] address;
+
+	reg dutpassed;	// Flag is set to false if any of the tests fail.
+
+	decoder1to32 DUT (out, enable, address);
+
+	initial begin
+		dutpassed = 1;
+
+		// Test Case 1: do not enable writing to any register.
+		enable = 0; address = 5'd14;
+		if (out != 0) begin
+			$display("Decoder Test Case 1 failed");
+			dutpassed = 0;
+		end //
+
+		// Test Case 2:
+		// Enable writing to one register only.
+		#5
+		enable = 1; address = 5'd14;
+		if (out[31:15] != 0 || out[14] != 1 || out[13:0] != 0) begin
+			$display("Decoder Test Case 2 failed");
+			dutpassed = 0;
+		end
+
+		#5
+
+		if (dutpassed ==1) begin
+			$display("All decoder tests passed.");
+		end
+	end //
+endmodule // decoder1to32Test

decoders.v

@@ -12,3 +12,9 @@ input[4:0]	address
 
 endmodule
 
+// Enable is set to be the least significant bit of out. The
+// value of address (which can be between 0 and 31) indicates
+// the number of bits out should be be shifted left by.
+
+// So, the decoder selects the register which is being written to (if any)
+// by using the value of adress.

makefile

@@ -0,0 +1,10 @@
+all: register_test mux_test decoder_test regfile_test
+
+register_test: register.t.v register.v
+	iverilog -Wall -o register_test register.t.v
+mux_test: multiplexer.t.v multiplexer.v
+	iverilog -Wall -o mux_test multiplexer.t.v
+decoder_test: decoders.t.v decoders.v
+	iverilog -Wall -o decoder_test decoders.t.v
+regfile_test: regfile.t.v regfile.v register.v multiplexer.v decoders.v
+	iverilog -Wall -o regfile_test regfile.t.v

multiplexer.t.v

@@ -0,0 +1,108 @@
+//--------------------------------
+// Test the multiplexer modules.
+//--------------------------------
+
+`include "multiplexer.v"
+
+// Test harness for multiplexer unit test modules.
+module multiplexerTestBenchHarness();
+	reg begintest0;
+	reg begintest1;
+	wire endtest0;
+	wire endtest1;
+	wire dutpassed0;
+	wire dutpassed1;
+
+	mux32to1by1Test test0 (begintest0, endtest0, dutpassed0);
+	mux32to32by1Test test1 (begintest1, endtest1, dutpassed1);
+
+	initial begin
+		begintest0 = 0;
+		begintest1 = 0;
+		#10;
+		begintest0 = 1;
+		begintest1 = 1;
+		#1000;
+	end
+
+	always @(posedge endtest0 && endtest1) begin
+		if (dutpassed0 == 1 || dutpassed1 == 1) begin
+			$display("All multiplexer tests passed.");
+		end
+	end
+
+endmodule // multiplexerTestBenchHarness
+
+// Unit test the 32:1 mux module.
+module mux32to1by1Test
+	(
+	input begintest,
+	output reg endtest,
+	output reg dutpassed
+	);
+	wire out;
+	reg[4:0] address;
+	reg[31:0] inputs;
+
+	mux32to1by1 DUT (out, address, inputs);
+
+	always @(posedge begintest) begin
+		endtest = 0;
+		dutpassed = 1;
+
+		// Test Case 1:
+		// Ensure that out is the same as the bit of the input at the 
+		// given address.
+		inputs = 32'h000FFF; address = 5'd9;
+		if (out != 1) begin
+			$display("32:1 mux Test Case 1 Failed.");
+			dutpassed = 0;
+		end
+
+		#5
+		endtest = 1;
+	end
+endmodule // mux32to1by1Test
+
+// Unit test the 32 wide 32 deep mux module.
+module mux32to32by1Test(
+	input begintest,
+	output reg endtest,
+	output reg dutpassed
+	);
+	wire[31:0] out;
+	reg[4:0] address;
+	reg[31:0] input0, input1, input2, input3, input4, input5, input6, input7, input8;
+	reg[31:0] input9, input10, input11, input12, input13, input14, input15, input16;
+	reg[31:0] input17, input18, input19, input20, input21, input22, input23, input24;
+	reg[31:0] input25, input26, input27, input28, input29, input30, input31;
+
+	mux32to1by32 DUT (out, address, input0, input1, input2, input3, input4, input5,
+		input6, input7, input8, input9, input10, input11, input12, input13, input14,
+		input15, input16, input17, input18, input19, input20, input21, input22, input23,
+		input24, input25, input26, input27, input28, input29, input30, input31);
+
+	always @(posedge begintest) begin
+		endtest = 0;
+		dutpassed = 1;
+
+		// Test Case 1:
+		// Ensure that the value chosen by the mux matches the value at the given address
+		address = 5'd20;
+		input0 = 32'd0; input1 = 32'd1; input2 = 32'd2; input3 = 32'd3; input4 = 32'd4;
+		input5 = 32'd5; input6 = 32'd6; input7 = 32'd7; input8 = 32'd8; input9 = 32'd9;
+		input10 = 32'd10; input11 = 32'd11; input12 = 32'd12; input13 = 32'd13; input14 = 32'd14;
+		input15 = 32'd15; input16 = 32'd16; input17 = 32'd17; input18 = 32'd18; input19 = 32'd19;
+		input20 = 32'd20; input21 = 32'd21; input22 = 32'd22; input23 = 32'd23; input24 = 32'd24;
+		input25 = 32'd25; input26 = 32'd26; input27 = 32'd27; input28 = 32'd28; input29 = 32'd29;
+		input30 = 32'd30; input31 = 32'd31;
+		if (out != 20) begin
+			$display("32 wide 32 deep mux Test Case 1 failed");
+			dutpassed = 0;
+		end
+
+		#5
+		endtest = 1;
+	end
+endmodule // mux32to32by1Test
+

multiplexer.v

@@ -0,0 +1,56 @@
+// A 32:1 multiplexer.
+module mux32to1by1
+(
+output out,
+input[4:0] address,
+input[31:0] inputs
+);
+	assign out = inputs[address];
+endmodule // mux32to1by1
+
+module mux32to1by32
+(
+output[31:0] out,
+input[4:0] address,
+input[31:0] input0, input1, input2, input3, input4, input5, input6, input7, input8,
+input[31:0] input9, input10, input11, input12, input13, input14, input15, input16,
+input[31:0] input17, input18, input19, input20, input21, input22, input23, input24,
+input[31:0] input25, input26, input27, input28, input29, input30, input31
+);
+
+	wire[31:0] mux[31:0];	// Create a 2D array of wires
+	assign mux[0] = input0;
+	assign mux[1] = input1;
+	assign mux[2] = input2;
+	assign mux[3] = input3;
+	assign mux[4] = input4;
+	assign mux[5] = input5;
+	assign mux[6] = input6;
+	assign mux[7] = input7;
+	assign mux[8] = input8;
+	assign mux[9] = input9;
+	assign mux[10] = input10;
+	assign mux[11] = input11;
+	assign mux[12] = input12;
+	assign mux[13] = input13;
+	assign mux[14] = input14;
+	assign mux[15] = input15;
+	assign mux[16] = input16;
+	assign mux[17] = input17;
+	assign mux[18] = input18;
+	assign mux[19] = input19;
+	assign mux[20] = input20;
+	assign mux[21] = input21;
+	assign mux[22] = input22;
+	assign mux[23] = input23;
+	assign mux[24] = input24;
+	assign mux[25] = input25;
+	assign mux[26] = input26;
+	assign mux[27] = input27;
+	assign mux[28] = input28;
+	assign mux[29] = input29;
+	assign mux[30] = input30;
+	assign mux[31] = input31;
+	assign out = mux[address];
+
+endmodule // mux32to1by32

regfile.t.v

@@ -3,6 +3,8 @@
 // or broken register files, and verifying that it correctly identifies each
 //------------------------------------------------------------------------------
 
+`include "regfile.v"
+
 module hw4testbenchharness();
 
   wire[31:0]	ReadData1;	// Data from first register read
@@ -109,23 +111,20 @@ output reg		Clk
 
   // Test Case 1: 
   //   Write '42' to register 2, verify with Read Ports 1 and 2
-  //   (Passes because example register file is hardwired to return 42)
   WriteRegister = 5'd2;
   WriteData = 32'd42;
   RegWrite = 1;
   ReadRegister1 = 5'd2;
   ReadRegister2 = 5'd2;
   #5 Clk=1; #5 Clk=0;	// Generate single clock pulse
 
-  // Verify expectations and report test result
   if((ReadData1 != 42) || (ReadData2 != 42)) begin
     dutpassed = 0;	// Set to 'false' on failure
     $display("Test Case 1 Failed");
   end
 
   // Test Case 2: 
   //   Write '15' to register 2, verify with Read Ports 1 and 2
-  //   (Fails with example register file, but should pass with yours)
   WriteRegister = 5'd2;
   WriteData = 32'd15;
   RegWrite = 1;
@@ -138,6 +137,35 @@ output reg		Clk
     $display("Test Case 2 Failed");
   end
 
+  // Test Case 3:
+  // Do not enable writing, check to ensure register
+  // data is not replaced by WriteData;
+  WriteRegister = 5'd2;
+  WriteData = 32'd20;
+  RegWrite = 0;
+  ReadRegister1 = 5'd2;
+  ReadRegister2 = 5'd2;
+  #5 Clk=1; #5 Clk=0;
+
+  if((ReadData1 != 15) || (ReadData2 != 15)) begin
+    dutpassed = 0;
+    $display("Test Case 3 Failed");
+  end
+
+  // Test Case 4:
+  // Attempt to write to the zero register.
+  // Ensure that the data value is still 32'b0.
+  WriteRegister = 5'd0;
+  WriteData = 32'd15;
+  RegWrite = 1;
+  ReadRegister1 = 5'd0;
+  ReadRegister2 = 5'd0;
+  #5 Clk=1; #5 Clk=0;
+
+  if((ReadData1 != 0 || ReadData2 != 0)) begin
+    dutpassed = 0;
+    $display("Test Case 4 Failed");
+  end
 
   // All done!  Wait a moment and signal test completion.
   #5