HW 4 Submission

decoders.v

@@ -8,7 +8,7 @@ input		enable,
 input[4:0]	address
 );
 
-    assign out = enable<<address; 
+    assign out = enable<<address; // shift enable bit over by addresss
 
 endmodule
 

mux.t.v

@@ -0,0 +1,48 @@
+`timescale 1 ns / 1 ps
+`include "mux.v"
+
+
+// This was used to check the functionality of the mux
+module testMultiplexer ();
+
+parameter size = 432;
+reg [size-1:0] inputs;
+wire out;
+reg [1:0] address;
+
+mux32to1by1 testingfour(out, address, inputs);
+
+initial begin
+
+// tests with just four-bit input and 2-bit address
+// tests were successful
+/*
+$display("Inputs | Address | Output ");
+inputs = 4'b0101; address = 2'b00; #1000
+$display("%b   | %b | %b ", inputs, address, out);
+
+inputs = 4'b0101; address = 2'b01; #1000
+$display("%b   | %b | %b ", inputs, address, out);
+
+inputs = 4'b0101; address = 2'b10; #1000
+$display("%b   | %b | %b ", inputs, address, out);
+
+inputs = 4'b0101; address = 2'b11; #1000
+$display("%b   | %b | %b ", inputs, address, out);
+
+$display("Inputs | Address | Output ");
+inputs = 4'b1010; address = 2'b00; #1000
+$display("%b   | %b | %b ", inputs, address, out);
+
+inputs = 4'b1010; address = 2'b01; #1000
+$display("%b   | %b | %b ", inputs, address, out);
+
+inputs = 4'b1010; address = 2'b10; #1000
+$display("%b   | %b | %b ", inputs, address, out);
+
+inputs = 4'b1010; address = 2'b11; #1000
+$display("%b   | %b | %b ", inputs, address, out);
+end
+*/
+
+endmodule

mux.v

@@ -0,0 +1,91 @@
+module mux32to1by1
+(
+output      out,
+input[1:0]  address,
+input[31:0] inputs
+);
+
+assign out=inputs[address];
+
+endmodule
+
+module mux32to1by32
+(
+output[31:0]  out,
+input[4:0]    address,
+input[31:0]   input0,
+input[31:0]    input1,
+input[31:0]    input2,
+input[31:0]    input3,
+input[31:0]    input4,
+input[31:0]    input5,
+input[31:0]    input6,
+input[31:0]    input7,
+input[31:0]    input8,
+input[31:0]    input9,
+input[31:0]    input10,
+input[31:0]    input11,
+input[31:0]    input12,
+input[31:0]    input13,
+input[31:0]    input14,
+input[31:0]    input15,
+input[31:0]    input16,
+input[31:0]    input17,
+input[31:0]    input18,
+input[31:0]    input19,
+input[31:0]    input20,
+input[31:0]    input21,
+input[31:0]    input22,
+input[31:0]    input23,
+input[31:0]    input24,
+input[31:0]    input25,
+input[31:0]    input26,
+input[31:0]    input27,
+input[31:0]    input28,
+input[31:0]    input29,
+input[31:0]    input30,
+input[31:0]    input31
+);
+
+
+  wire[31:0] mux[31:0];			// Create a 2D array of wires
+
+  // Repeat 31 times...
+	assign mux[0] = input0;		// Connect the sources of the array
+	assign mux[1] = input1;		
+	assign mux[2] = input2;		
+	assign mux[3] = input3;
+	assign mux[4] = input4;				
+	assign mux[5] = input5;		
+	assign mux[6] = input6;		
+	assign mux[7] = input7;		
+	assign mux[8] = input8;		
+	assign mux[9] = input9;		
+	assign mux[10] = input10;		
+	assign mux[11] = input11;
+	assign mux[12] = input12;
+	assign mux[13] = input13;		
+	assign mux[14] = input14;		
+	assign mux[15] = input15;		
+	assign mux[16] = input16;		
+	assign mux[17] = input17;					
+	assign mux[18] = input18;		
+	assign mux[19] = input19;		
+	assign mux[20] = input20;		
+	assign mux[21] = input21;		
+	assign mux[22] = input22;		
+	assign mux[23] = input23;		
+	assign mux[24] = input24;		
+	assign mux[25] = input25;		
+	assign mux[26] = input26;		
+	assign mux[27] = input27;		
+	assign mux[28] = input28;		
+	assign mux[29] = input29;		
+	assign mux[30] = input30;		
+	assign mux[31] = input31;		
+
+
+  assign out = mux[address];	// Connect the output of the array
+
+
+endmodule

regfile.t.v

@@ -3,6 +3,8 @@
 // or broken register files, and verifying that it correctly identifies each
 //------------------------------------------------------------------------------
 
+`include "regfile.v"
+
 module hw4testbenchharness();
 
   wire[31:0]	ReadData1;	// Data from first register read
@@ -110,6 +112,7 @@ output reg		Clk
   // Test Case 1: 
   //   Write '42' to register 2, verify with Read Ports 1 and 2
   //   (Passes because example register file is hardwired to return 42)
+/*
   WriteRegister = 5'd2;
   WriteData = 32'd42;
   RegWrite = 1;
@@ -137,6 +140,94 @@ output reg		Clk
     dutpassed = 0;
     $display("Test Case 2 Failed");
   end
+*/
+
+// Test Case 3: RegWrite is broken, Register is always written to
+// Write '9' to register 5, and RegWrite is on (confirm is working)
+	WriteRegister = 5'd5;
+	WriteData = 32'd9;
+	RegWrite = 1;
+	ReadRegister1 = 5'd5;
+	ReadRegister2 = 5'd5;
+  #5 Clk=1; #5 Clk=0;
+  if((ReadData1 != WriteData) || (ReadData2 != 9)) begin
+    dutpassed = 0;
+    $display("Test Case 3 Failed");
+  end
+
+// then see if, when regwrite is off, will the value still get transferred to readregister
+	WriteRegister = 5'd10;
+	WriteData = 32'd12;
+	RegWrite = 0;
+	ReadRegister1 = 5'd10;
+	ReadRegister2 = 5'd10;
+  #5 Clk=1; #5 Clk=0;
+  if((ReadData1 == WriteData) || (ReadData2 == WriteData)) begin
+    dutpassed = 0;
+    $display("Test Case 3 Failed");
+  end
+
+// Test Case 4: Decoder is broken. All registers are written to.
+// set one register correctly. then, write a different value to a different register. if both registers are now set to the new value, your decoder is broken.
+
+	WriteRegister = 5'd2;
+	WriteData = 32'd22;
+	RegWrite = 1;
+	ReadRegister1 = 5'd2;
+  #5 Clk=1; #5 Clk=0;
+  if(ReadData1 == WriteData)begin
+    dutpassed = 0;
+    $display("Test Case 4 Failed");
+  end
+
+	WriteRegister = 5'd3;
+	WriteData = 32'd23;
+	RegWrite = 1;
+	ReadRegister2 = 5'd3;
+  #5 Clk=1; #5 Clk=0;
+  if(ReadData1 == ReadData2)begin
+    dutpassed = 0;
+    $display("Test Case 4 Failed");
+  end
+
+
+//Test Case 5: Register Zero returns something other than zero
+	WriteRegister = 5'd0;
+	WriteData = 32'd22;
+	RegWrite = 1;
+	ReadRegister1 = 5'd0;
+  #5 Clk=1; #5 Clk=0;
+  if((ReadData1 != 0))begin
+    dutpassed = 0;
+    $display("Test Case 5 Failed");
+  end
+
+// Test Case 6: Ports 1 or 2 are broken and don't switch which register they read
+	WriteRegister = 5'd5;
+	WriteData = 32'd22;
+	RegWrite = 1;
+	ReadRegister1 = 5'd5;
+  #5 Clk=1; #5 Clk=0;
+  if((ReadRegister1 != WriteRegister))begin
+    dutpassed = 0;
+    $display("Test Case 5 Failed");
+  end
+
+	WriteRegister = 5'd6;
+	WriteData = 32'd22;
+	RegWrite = 1;
+	ReadRegister2 = 5'd6;
+  #5 Clk=1; #5 Clk=0;
+  if((ReadRegister2 != WriteRegister))begin
+    dutpassed = 0;
+    $display("Test Case 5 Failed");
+  end
+
+
+// Test Case Final: Return true if everything works
+if (dutpassed == 1) begin
+	$display("True");
+end
 
 
   // All done!  Wait a moment and signal test completion.
@@ -145,4 +236,4 @@ output reg		Clk
 
 end
 
-endmodule
+endmodule

regfile.v

@@ -6,6 +6,11 @@
 //   1 synchronous, positive edge triggered write port
 //------------------------------------------------------------------------------
 
+
+`include "register.v"
+`include "mux.v"
+`include "decoders.v"
+
 module regfile
 (
 output[31:0]	ReadData1,	// Contents of first register read
@@ -18,10 +23,83 @@ input		RegWrite,	// Enable writing of register when High
 input		Clk		// Clock (Positive Edge Triggered)
 );
 
-  // These two lines are clearly wrong.  They are included to showcase how the 
-  // test harness works. Delete them after you understand the testing process, 
-  // and replace them with your actual code.
-  assign ReadData1 = 42;
-  assign ReadData2 = 42;
+// create the decoder
+	wire[31:0] decoderout;
+	decoder1to32 decode(decoderout, RegWrite, WriteRegister);
+
+	// going to want to generate 32 registers, where register0 always outputs 0 and the other registers all behave normally.
+
+	// also need to create the outputs of the register/inputs for the mux
+	wire [31:0] InForMux0;
+	wire [31:0] InForMux1;
+	wire [31:0] InForMux2;
+	wire [31:0] InForMux3;
+	wire [31:0] InForMux4;
+	wire [31:0] InForMux5;
+	wire [31:0] InForMux6;
+	wire [31:0] InForMux7;
+	wire [31:0] InForMux8;
+	wire [31:0] InForMux9;
+	wire [31:0] InForMux10;
+	wire [31:0] InForMux11;
+	wire [31:0] InForMux12;
+	wire [31:0] InForMux13;
+	wire [31:0] InForMux14;
+	wire [31:0] InForMux15;
+	wire [31:0] InForMux16;
+	wire [31:0] InForMux17;
+	wire [31:0] InForMux18;
+	wire [31:0] InForMux19;
+	wire [31:0] InForMux20;
+	wire [31:0] InForMux21;
+	wire [31:0] InForMux22;
+	wire [31:0] InForMux23;
+	wire [31:0] InForMux24;
+	wire [31:0] InForMux25;
+	wire [31:0] InForMux26;
+	wire [31:0] InForMux27;
+	wire [31:0] InForMux28;
+	wire [31:0] InForMux29;
+	wire [31:0] InForMux30;
+	wire [31:0] InForMux31;
+
+	register32zero  reg0(InForMux0, WriteData, decoderout[0], Clk);
+	register32 	reg1(InForMux1, WriteData, decoderout[1], Clk);
+	register32 	reg2(InForMux2, WriteData, decoderout[2], Clk);
+	register32 	reg3(InForMux3, WriteData, decoderout[3], Clk);
+	register32 	reg4(InForMux4, WriteData, decoderout[4], Clk);
+	register32 	reg5(InForMux5, WriteData, decoderout[5], Clk);
+	register32 	reg6(InForMux6, WriteData, decoderout[6], Clk);
+	register32 	reg7(InForMux7, WriteData, decoderout[7], Clk);
+	register32 	reg8(InForMux8, WriteData, decoderout[8], Clk);
+	register32 	reg9(InForMux9, WriteData, decoderout[9], Clk);
+	register32 	reg10(InForMux10, WriteData, decoderout[10], Clk);
+	register32 	reg11(InForMux11, WriteData, decoderout[11], Clk);
+	register32 	reg12(InForMux12, WriteData, decoderout[12], Clk);
+	register32 	reg13(InForMux13, WriteData, decoderout[13], Clk);
+	register32 	reg14(InForMux14, WriteData, decoderout[14], Clk);
+	register32 	reg15(InForMux15, WriteData, decoderout[15], Clk);
+	register32 	reg16(InForMux16, WriteData, decoderout[16], Clk);
+	register32 	reg17(InForMux17, WriteData, decoderout[17], Clk);
+	register32 	reg18(InForMux18, WriteData, decoderout[18], Clk);
+	register32 	reg19(InForMux19, WriteData, decoderout[19], Clk);
+	register32 	reg20(InForMux20, WriteData, decoderout[20], Clk);
+	register32 	reg21(InForMux21, WriteData, decoderout[21], Clk);
+	register32 	reg22(InForMux22, WriteData, decoderout[22], Clk);
+	register32 	reg23(InForMux23, WriteData, decoderout[23], Clk);
+	register32 	reg24(InForMux24, WriteData, decoderout[24], Clk);
+	register32 	reg25(InForMux25, WriteData, decoderout[25], Clk);
+	register32 	reg26(InForMux26, WriteData, decoderout[26], Clk);
+	register32 	reg27(InForMux27, WriteData, decoderout[27], Clk);
+	register32 	reg28(InForMux28, WriteData, decoderout[28], Clk);
+	register32 	reg29(InForMux29, WriteData, decoderout[29], Clk);
+	register32 	reg30(InForMux30, WriteData, decoderout[30], Clk);
+	register32 	reg31(InForMux31, WriteData, decoderout[31], Clk);
+
+
+// Use the muxes to get two outputs - ReadData1 and ReadData2
+	mux32to1by32 mux1(ReadData1, ReadRegister1, InForMux0, InForMux1, InForMux2, InForMux3, InForMux4, InForMux5, InForMux6, InForMux7, InForMux8, InForMux9, InForMux10, InForMux11, InForMux12, InForMux13, InForMux14, InForMux15, InForMux16, InForMux17, InForMux18, InForMux19, InForMux20, InForMux21, InForMux22, InForMux23, InForMux24, InForMux25, InForMux26, InForMux27, InForMux28, InForMux29, InForMux30, InForMux31);
+
+	mux32to1by32 mux2(ReadData2, ReadRegister2, InForMux0, InForMux1, InForMux2, InForMux3, InForMux4, InForMux5, InForMux6, InForMux7, InForMux8, InForMux9, InForMux10, InForMux11, InForMux12, InForMux13, InForMux14, InForMux15, InForMux16, InForMux17, InForMux18, InForMux19, InForMux20, InForMux21, InForMux22, InForMux23, InForMux24, InForMux25, InForMux26, InForMux27, InForMux28, InForMux29, InForMux30, InForMux31);
 
-endmodule
+endmodule