merge mxint_linear #229
merge mxint_linear #229
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@firemountain154B it seems like |
Plan to finish it today |
| def _trigger(self): | ||
| return self.valid.value == 1 and self.ready.value == 1 | ||
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| # async def _driver_send(self, data) -> None: |
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Can we just delete this?
| /* | ||
| Module : mxint_accumulator | ||
| Description : The accumulator for mxint. | ||
| When inputing different exponent, the mantissa will cast to the same bitwidth then accumulate. |
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Is this a lossy behaviour? If it is, it might worth to add a few more lines to explain its behaviour? I assume this is the module that aligns the exponent first?
| .out_data(mdata_out[i]) | ||
| ); | ||
| end | ||
| // for (genvar i = 0; i < BLOCK_SIZE; i++) begin |
| data_for_out_ready = buffer_data_for_out_ready; | ||
| end | ||
| end else begin | ||
| if (FIFO_DEPTH == 0) begin : register |
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what is this FIFO depth here?
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Is this a circular buffer? If it is, maybe add some comments at the top of the file.
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what is a or_tree... this is confusing...
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