RV_GO!!!!!

Introduction

This is a RV32I 5-stage in-order pipelined CPU, aiming at covering all the digital IC flow (from system level to final sign-off).

Todo

• Cocotb test
• C test
• Handle hazzard, pipeline flush, etc.
• Support multiply/divide (32M)
• Add AXI4 Bus
• Support interupt
• Add more peris: JTAG, UART, I2C, SPI
• Add scan-chain for DFT purpose

Documentation

wait to add

Reference

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