VSD RISC-V SoC Tapeout Program

Hands-on SoC design journey from RTL to GDSII using open-source EDA. Part of the VSD RISC-V Reference SoC Tapeout Program, covering RTL simulation, synthesis, gate level simulation (GLS), STA, floorplan, placement, routing, and timing closure — building a unique RISC-V SoC ready for tapeout

Links to Detailed Logs

Expand to view my progress logs

Week	Topics Covered	Status
Week 0	Chip Modelling and Tool Installation	✅ Done
Week 1	RTL Design and Synthesis	✅ Done
Week 2	System-on-Chip and BabySoC Functional Modelling	✅ Done
Week 3	Gate-Level Simulation (GLS) and Static Timing Analysis(STA)	🔜 Planned
Week 4	...	🔜 Planned
Week 5	...	🔜 Planned
Week 6	...	🔜 Planned
Week 7	...	🔜 Planned
Week 8	...	🔜 Planned
Week 9	...	🔜 Planned
Week 10	...	🔜 Planned

Program Objective

• Learn end-to-end RISC-V SoC design and tapeout flow using open-source EDA tools.
• Explore RTL design, simulation, synthesis, STA, and physical design concepts.
• Gain hands-on exposure to GLS, PnR, timing closure, and sign-off practices.
• Apply knowledge in a structured week-by-week learning plan (from spec → GDSII).
• Build a unique reference SoC project, documented for reproducibility and tapeout readiness.

Program Outcomes

This section will be updated after each week’s section is completed.

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Tech Stack

• Languages: Verilog, SystemVerilog
• Tools: Yosys, iverilog, GTKwave, .......
• Platform: Ubuntu on VirtualBox

Stay tuned as I document each week with logs, screenshots, and results!