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Add flow diagram, hardware details to excercise LPM mode.

Signed-off-by: Udit Kumar <u-kumar1@ti.com>
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1. Only A core as suspend master supported and tested with Linux.
2. The LPM feature is not supported on HS-SE variant J784S4.
3. If PCIe is being used, the resume latency increases by 1 sec for every PCIe instance, If EP is not connected.

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EP?.. Is it better to have this as Endpoint, wouldn't it be confusing EP alone ?

2. The LPM feature is not supported on HS-SE variant J784S4.
3. If PCIe is being used, the resume latency increases by 1 sec for every PCIe instance, If EP is not connected.
4. Remote core firmwares are getting loaded by Linux on resume.
5. MCU domain R5 core, cannot be used in split mode.

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This core cannot be used in split mode only to exercise LPM sequence correct ? So, isn't this a known issue rather than limitation.

Software modifications
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TI’s K3 Jacinto family of SOCs have a concept of boardcfg that can be used to configure certain parameters at build time.
By default, SDK supports SOC_OFF mode.

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By default, SDK supports SOC_OFF mode.
SDK supports both, but SOC_OFF is enabled/selected by default. So, may be something like below
By default, SOC_OFF mode enabled by default in SDK.

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8 participants