Opcodes

Note: This is the list of opcodes as they currently stand. it is not a recommendation, or a proposal. It is intended mostly as a reference, particularly to aid in discussions about the quality and extent of the current design.

In particular, it should be noted that the intention is to revise and reorder the opcodes.

Additional Note: This list has not yet been checked for accuracy.

Opcode	Menomic	Length (Bytes)	Description Summary
00h	NOP	1	No OPeration Does nothing.
01h	INC ACC	1	Fixed register Increment Increments the value stored in ACC by one.
02h	MOV &R1⇒&R2	2	Move indirect Free-register Moves the data at the address pointed to by R1, and moves it to the address in R2.
03h	MOV A⇒nn	2	Move direct fixed-register (A) Moves the contents of A to the address at nn.
04h	MOV &nn⇒A	2	Move fixed-register (A) indirect Moves the contents of the address at nn into A.
05h	MOV nn⇒A	2	Move literal fixed-register (A) Moves nn into A.
06h	ADD R1,R2⇒ACC	2	ADD partial free-register, result fixed ACC Adds the values contained in the register R1 and R2, and puts the results into ACC
07h	SWP R1⇔R2	2	SWP free-register Swaps the contents of registers R1 and R2. Such that `R1=R2, and `R2=R1.
Opcode	Menomic	Length (Bytes)	Description Summary
08h	SWP A⇔B	1	SWP fixed-register (A, B) Swaps the contents of registers A and B. Such that `A=B, and `B=A.
09h	ADD A,B⇒ACC	1	ADD fixed-register, result fixed ACC Adds the values contained in the registers A and B, and puts the results into ACC
0Ah	SHW A	1	SHW fixed-register (Debug) Presents the contents of register A through the Debugging channel.
0Bh	JMP nn or MOV nn⇒IP	2	Unconditional Jump with fixed RET MOV litteral fixed-register (IP) Sets the IP register equal to nn
0Ch	JNZ RET,nn or MNZ RET,nn⇒IP	2	Conditional Jump MOV litteral fixed-register (IP) Sets the IP register equal to nn
0Dh	LES A,B⇒RET	1	Less than If *A* is less than *B*, then *RET* is set to a non-zero value, otherwise *RET* is set to zero.
0Eh	MNZ R1,R2⇒nn	3	Free-register Conditional move If *R1* is non-zero, move the contents *R2* to the address *nn*
0Fh	MOV R1⇒R2	2	Move Free-register Moves the data in R1, and moves it into R2.
Opcode	Menomic	Length (Bytes)	Description Summary
10h	NOT R1⇒R2	2	Bitwise NOT Sets *R2* to the bitwise-not of *R1*
11h	AND R1,R2⇒RET	2	Bitwise AND Sets RET to the bitwise-and of R1 and R2
12h	OR R1,R2⇒RET	2	Bitwise OR Sets RET to the bitwise-or of R1 and R2
13h	XOR R1,R2⇒RET	2	Bitwise XOR Sets RET to the bitwise-xor of R1 and R2
14h	SHL R1,R2⇒RET	2	Shift left Sets RET to the value of R1 shifted left R2 positions
15h	SHR R1,R2⇒RET	2	Shift right Sets RET to the value of R1 shifted right R2 positions
16h	SRE R1,R2⇒RET	2	Shift right, with sign extension Sets RET to the value of R1 shifted right R2 positions, while extending the sign bit (MSB)
17h	IN R1⇒R2	2	Port I/O Read Reads from the I/O port R1, and places the result in R2
Opcode	Menomic	Length (Bytes)	Description Summary
18h	OUT R1,R2	2	Port I/O Write Writes R2 to I/O port R1
19h	MUL R1,R2⇒RET	2	Multiply free-register Multiplies R1 by R2, and places the result in RET
1Ah	SUB R1,R2⇒ACC	2	Subtract free-register Subtracts R2 from R1, and places the result in ACC
1Bh	MOD R1,R2⇒RET	2	Modulo free-register, result in RET sets RET to the Modulo of R1 and R2
1Ch	MOD R1,R2⇒ACC	2	Free-register Modulo, result in ACC Sets ACC to the Modulo of R1 and R2
1Dh	DIV R1,R2⇒ACC	2	Free-register Division, result in ACC Divides R1 by R2, and places the result in RET
1Eh	MUL R1,R2⇒ACC	2	Free-register Multiply, result in ACC Multiplies R1 by R2, and places the result in ACC
1Fh	DEC ACC	1	Fixed-register Decrement Decrements the value stored in ACC by one.
Opcode	Menomic	Length (Bytes)	Description Summary
20h	SUB R1,R2⇒RET	2	Free-register Subtraction Subtracts the contents R2 from R1, and puts the result in RET.
21h	MOV nn⇒B	2	Fixed-register literal move Moves the value nn into B.
22h	MOV &nn⇒B	2	Fixed-register indirect move Moves the value stored in the address nn into B.
23h	MOV B⇒nn	2	Fixed-register move direct Moves the value in B into the address indicated by nn.
24h	LMOV R1,R2⇒R3,R4	3	Free-register direct Long Move Takes the value R2 bytes into segment R1, and places it R4 bytes into segment R3.
25h	LJMP R1,R2	2	Free-register Long jump Set the Segment Pointer to R1, and the Instruction Pointer to R2. Execution will continue from there as normal.
26h	ROL R1,R2⇒RET	2	Free-register Roll Left Rolls the bit-pattern contained in R1 left by the number of positions indicated by the value in R2. Rolling is similar to shifting, save that bits shifted off one end are re-inserted at the other end, rather than being lost
27h	ROR R1,R2⇒RET	2	Free-register Roll Right Rolls the bit-pattern contained in R1 right by the number of positions indicated by the value in R2. Rolling is similar to shifting, save that bits shifted off one end are re-inserted at the other end, rather than being lost
Opcode	Menomic	Length (Bytes)	Description Summary
28h	LOAD R1⇒R2	2	Load, free-register the load instrution, used to load data from an address into a register
29h	LOAD nn⇒R2	3	Load, partial free-register, address the load instrution, used to load data from an address into a register
2Ah	STOR R1⇒R2	2	Store, free-register the store instrution, used to store data from a register into an address.
2Bh	STOR R1⇒nn	3	Store, partial free-register, address the store instrution, used to store data from a register into an address.
2Ch			(Reserved) (Unused)
2Dh			(Reserved) (Unused)
2Eh			(Reserved) (Unused)
2Fh			(Reserved) (Unused)
Opcode	Menomic	Length (Bytes)	Description Summary
30h — 9Fh			(Reserved) (Unused)
Opcode	Menomic	Length (Bytes)	Description Summary
A0h	EQL R1,R2⇒;RET	2	Equality test If R1 and R2 are bitwise identical, set RET to non-zero. otherwise set RET to zero
A1h	SHW R	2	SHW free-register (Debug) Presents the contents of register R through the Debugging channel.
A2h	DIV R1,R2⇒RET	2	Divide free-register Divides R1 by R2, and places the result in RET
A3h	GTR A,B⇒RET	1	Greater Than, fixed register (A, B) If *A* is greater than *B*, then *RET* is set to a non-zero value, otherwise *RET* is set to zero.
A4h	ADD R1,R2⇒RET	2	Free-register Addition Adds the contents of R1 and R2, and puts the result in RET
A5h	SUB A,B⇒RET	1	Fixed-register (A,B) subtraction Subtracts the contents R2 from R1, and puts the result in RET
A6h	ADD A,B⇒RET	1	Fixed-register Addition Adds the contents of A and B, and puts the result in RET
A7h	SUB A,B⇒ACC	1	Fixed-register Subtraction Subtracts the contents B from A, and puts the result in ACC
Opcode	Menomic	Length (Bytes)	Description Summary
A8h — F7h			(Reserved) (Unused)
Opcode	Menomic	Length (Bytes)	Description Summary
F8h			(Reserved) (Unused)
F9h			(Reserved) (Unused)
FAh			(Reserved) (Unused)
ABh			(Reserved) (Unused)
FCh			(Reserved) (Unused)
FDh			(Reserved) (Unused)
FEh			(Reserved) (Unused)
FFh	HLT	1	Halt Halts the machine.