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Throw an exception if the user tries to render a trace without stepping the simulation Run Python tests #145: Pull request #472 opened by gaborszita
1m 23s gaborszita:sim-trace-error-no-step
gaborszita:sim-trace-error-no-step
1m 23s
Add readability aliases for Gate.op_param. These aliases assign nam… Build and publish release #79: Commit 137ff35 pushed by fdxmw
14s development
development
14s
Add readability aliases for Gate.op_param. These aliases assign nam… Run Python tests #144: Commit 137ff35 pushed by fdxmw
1m 25s development
development
1m 25s
Add documentation and examples for Const.val, `Register.reset_value… Build and publish release #78: Commit 0a57cd4 pushed by fdxmw
17s development
development
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Add documentation and examples for Const.val, `Register.reset_value… Run Python tests #143: Commit 0a57cd4 pushed by fdxmw
1m 14s development
development
1m 14s
Fix a typo in CHANGELOG.md's release notes for 0.12. Build and publish release #77: Commit ef456b6 pushed by fdxmw
19s development
development
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Fix a typo in CHANGELOG.md's release notes for 0.12. Run Python tests #142: Commit ef456b6 pushed by fdxmw
1m 10s development
development
1m 10s
Build and publish release Build and publish release #76: by fdxmw
4m 16s 0.12
0.12
4m 16s
Run Python tests Run Python tests #141: by fdxmw
1m 12s 0.12
0.12
1m 12s
Update CHANGELOG.md for 0.12 release Build and publish release #75: Commit 5ad9ed6 pushed by fdxmw
20s development
development
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Update CHANGELOG.md for 0.12 release Run Python tests #140: Commit 5ad9ed6 pushed by fdxmw
1m 18s development
development
1m 18s
Update output_to_verilog to inline temporary wires, using `GateGrap… Build and publish release #74: Commit 98d2b5c pushed by fdxmw
18s development
development
18s
Update output_to_verilog to inline temporary wires, using `GateGrap… Run Python tests #139: Commit 98d2b5c pushed by fdxmw
1m 14s development
development
1m 14s
Update output_to_verilog to inline temporary wires, using GateGraph: Run Python tests #138: Pull request #471 synchronize by fdxmw
1m 17s fdxmw:verilog
fdxmw:verilog
1m 17s
Update output_to_verilog to inline temporary wires, using GateGraph: Run Python tests #137: Pull request #471 synchronize by fdxmw
1m 13s fdxmw:verilog
fdxmw:verilog
1m 13s
Update output_to_verilog to inline temporary wires, using GateGraph: Run Python tests #136: Pull request #471 synchronize by fdxmw
1m 13s fdxmw:verilog
fdxmw:verilog
1m 13s
Update output_to_verilog to inline temporary wires, using GateGraph: Run Python tests #135: Pull request #471 synchronize by fdxmw
1m 12s fdxmw:verilog
fdxmw:verilog
1m 12s
Update output_to_verilog to inline temporary wires, using GateGraph: Run Python tests #134: Pull request #471 synchronize by fdxmw
1m 11s fdxmw:verilog
fdxmw:verilog
1m 11s
Update output_to_verilog to inline temporary wires, using GateGraph: Run Python tests #133: Pull request #471 synchronize by fdxmw
1m 13s fdxmw:verilog
fdxmw:verilog
1m 13s
Update output_to_verilog to inline temporary wires, using GateGraph: Run Python tests #132: Pull request #471 opened by fdxmw
1m 13s fdxmw:verilog
fdxmw:verilog
1m 13s
Initial implementation of GateGraph, an alternative PyRTL logic rep… Run Python tests #131: Commit 3deeedd pushed by fdxmw
1m 12s development
development
1m 12s
Initial implementation of GateGraph, an alternative PyRTL logic rep… Build and publish release #73: Commit 3deeedd pushed by fdxmw
12s development
development
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Initial implementation of GateGraph, an alternative PyRTL logic representation Run Python tests #130: Pull request #470 synchronize by fdxmw
1m 16s fdxmw:gate
fdxmw:gate
1m 16s
Initial implementation of GateGraph, an alternative PyRTL logic representation Run Python tests #129: Pull request #470 synchronize by fdxmw
1m 9s fdxmw:gate
fdxmw:gate
1m 9s
Initial implementation of GateGraph, an alternative PyRTL logic representation Run Python tests #128: Pull request #470 synchronize by fdxmw
1m 20s fdxmw:gate
fdxmw:gate
1m 20s