Initial implementation of GateGraph, an alternative PyRTL logic representation
#470
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…resentation: `GateGraph` attempts to address several issues with PyRTL's standard `WireVector` and `LogicNet` representation: 1. A `GateGraph` can be directly traversed, without the help of side data structures like the `wire_src_dict` and `wire_sink_dict` returned by `net_connections`. 2. `GateGraph` builds a graph where each node is a `Gate`, and the edges are all references to other `Gates`. By using only one node type, rather than two (`WireVector`, `LogicNet`), it becomes easier to work with the nodes in a `GateGraph`, because every node is the same type, with the same interface. 3. `GateGraph` decouples the user interface and the internal representation. Users directly instantiate `WireVectors` as they build circuits. A user that is only building circuits should never interact with a `GateGraph` or a `Gate`. Users should only interact with `GateGraph` when they need reflection, which typically happens when writing an analysis or optimization pass. Another advantage of this decoupling is that `Gate` does not need to support `WireVector`'s quality-of-life features for users, like inferring bitwidth from assignment.
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* `dest_fanout` -> `dests` * `dest_name` -> `name` * `dest_bitwidth` -> `bitwidth` * `dest_is_output` -> `is_output Add documentation on the differences between `LogicNet.dests` and `Gate.dests`. Minor other documentation improvements.
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I'm planning to merge this pull request tomorrow, so let me know soon if you have comments. |
…s to. I'd rather not have this bridge between the two representations, if possible. It should (eventually) be possible to do everything with only the new `Gate` representation. This also adds some more documentation pointers to `GateGraph`.
…'s easier to perform unions and intersections. Add more useful sets of `Gates` like `inputs`, `registers`, etc.
…mem_writes`. Also improve documentation: - Explain why `Gate` is implemented separately, rather than as a part of `WireVector`. - Don't publish documentation for `Gate.__init__`, as it should only be called by `GateGraph`. - Add more examples.
…es between `LogicNet.dests` and `Gate.dests`.
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GateGraphis an alternative PyRTL logic representation that attempts to address several issues with PyRTL's standardWireVectorandLogicNetrepresentation:A
GateGraphcan be directly traversed, without the help of side data structures like thewire_src_dictandwire_sink_dictreturned bynet_connections.GateGraphbuilds a graph where each node is aGate, and the edges are all references to otherGates. By using only one node type, rather than two (WireVector,LogicNet), it becomes easier to work with the nodes in aGateGraph, because every node is the same type, with the same interface.GateGraphdecouples the user interface and the internal representation. Users directly instantiateWireVectorsas they build circuits. A user that is only building circuits should never interact with aGateGraphor aGate. Users should only interact withGateGraphwhen they need reflection, which typically happens when writing an analysis or optimization pass.Another advantage of this decoupling is that
Gatedoes not need to supportWireVector's quality-of-life features for users, like inferring bitwidth from assignment.I'm migrating
output_to_verilogto use thisGateGraphrepresentation in a separate change.