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Eliminate double inverts in pyrtl.optimize #462
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Eliminate double inverts in pyrtl.optimize #462
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Codecov ReportAll modified and coverable lines are covered by tests ✅
Additional details and impacted files@@ Coverage Diff @@
## development #462 +/- ##
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+ Coverage 91.7% 92.0% +0.3%
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Files 24 24
Lines 6403 6470 +67
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+ Hits 5866 5946 +80
+ Misses 537 524 -13 ☔ View full report in Codecov by Sentry. 🚀 New features to boost your workflow:
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fdxmw
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Thank you for fixing this issue! A couple high-level comments before we get into coding details:
- O(N^2) nested
forloops overblock.logicshould generally be avoided in passes because they don't scale well as the number of nets increases - the pass will take too long to run. It seems possible to iterate overblock.logiconce and build a list of all the inverter chains in the block (see how other passes create a_ProducerListfor example). Then I think we can iterate over that list and decide if each inverter chain can be simplified? - This really needs a test :) Some test cases that come to mind:
- Chains of 1, 2, 3, and 4 inverters (even numbers of inverters should be removed, and odd numbers of inverters should be simplified to one inverter)
- A chain of 2 inverters with another user of the first inverter's output (should not be simplified)
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All addressed |
fdxmw
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Please start with the comments on line 109 and 81 first. If those can be addressed, they will probably make many other comments obsolete. Thank you for improving this code!
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I will fix these next week, I was busy this weekend. |
Sounds great, no rush! Let me know if you have any questions about my comments, happy to discuss. |
fdxmw
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Overall structure of this pull request looks great, so we are on to fine details at this point. We're almost there, thank you for your patience!
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Sorry for not squashing my commits, I forgot I already had commits locally when I pushed. |
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This should be the last round of comments, thank you for your patience!
fdxmw
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Looks great, thank you for all your effort on this pull request!
Closes #447
Example: