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Affinemapping with not working regression test #66

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9c27bc2
reviewed ImplementTaskDesignSpace
ZTTTX Jun 6, 2023
db5b079
Reviewed ImplementTaskDesignSpace
ZTTTX Jun 6, 2023
01bc0d9
formatted
ZTTTX Jun 6, 2023
af00d86
Formatted
ZTTTX Jun 6, 2023
dea8043
Formatted_ver2
ZTTTX Jun 6, 2023
19257db
Formatted_ver3
ZTTTX Jun 6, 2023
0d1b4e1
partial done emit cpp
ZTTTX Jun 6, 2023
139c92a
partial done emit cpp with annotation
ZTTTX Jun 6, 2023
5abba1c
c emit work with include
ZTTTX Jun 7, 2023
654b8b3
c emit include bug fix
ZTTTX Jun 7, 2023
99f635d
c emit include v1.1
ZTTTX Jun 7, 2023
daf2687
v1.2
ZTTTX Jun 7, 2023
aaeeefb
v1.3
ZTTTX Jun 7, 2023
98e7cb8
Merge branch 'awakening' of https://github.com/hanchenye/scalehls int…
ZTTTX Jun 8, 2023
ddc4bd9
cemit v2.0, added include check
ZTTTX Jun 8, 2023
326c047
cemit include check v2.0
ZTTTX Jun 9, 2023
7bd31cb
added regression test
ZTTTX Jun 9, 2023
b9c4252
v3.1
ZTTTX Jun 9, 2023
4dbe45d
v3.2
ZTTTX Jun 9, 2023
5477f7b
v3.3
ZTTTX Jun 9, 2023
471bd78
v3.4
ZTTTX Jun 9, 2023
10b86eb
v3.5
ZTTTX Jun 9, 2023
91ee80e
v3.6
ZTTTX Jun 9, 2023
b114a03
fixed print issue
ZTTTX Jun 10, 2023
30f6d71
fixed bug
ZTTTX Jun 10, 2023
c4dd762
Merge branch 'awakening' of https://github.com/hanchenye/scalehls int…
ZTTTX Jun 19, 2023
2d19380
affinemap branch, regression test not working
ZTTTX Jun 22, 2023
3044c9b
not working regression test
ZTTTX Jun 22, 2023
b678705
removed regression test
ZTTTX Jun 22, 2023
e5e06ee
v1
ZTTTX Jun 22, 2023
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8 changes: 4 additions & 4 deletions include/scalehls/Dialect/HLS/IR/HLSUIPOps.td
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Original file line number Diff line number Diff line change
Expand Up @@ -65,17 +65,17 @@ def InstanceOp : HLSOp<"uip.instance", [
}];
}

def PortOp : HLSOp<"uip.port", [Symbol, HasParent<"DeclareOp">]> {
def PortOp : HLSOp<"uip.port", [AttrSizedOperandSegments, Symbol, HasParent<"DeclareOp">]> {
let summary = "Declare a port of an IP";

let arguments = (ins TypeType:$type, Variadic<AnyType>:$sizes,
MemRefLayoutAttrInterface:$layout, PortKindAttr:$kind,
MemRefLayoutAttrInterface:$layout, PortKindAttr:$kind, Variadic<AnyType>:$symbol_ref,
OptionalAttr<TypedAttrInterface>:$value, SymbolNameAttr:$sym_name);
let results = (outs PortType:$result);

let assemblyFormat = [{
$sym_name $kind `type` $type `sizes` `(` $sizes `)` $layout attr-dict
`:` functional-type($sizes, $result)
$sym_name $kind `type` $type `sizes` `(` $sizes `)` `symbol_ref` `(` $symbol_ref `)` `(` type($symbol_ref) `)` $layout attr-dict
`:` functional-type($sizes, $result)
}];
}

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10 changes: 5 additions & 5 deletions test/EmitHLSCpp/test-instanceOp.mlir
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Expand Up @@ -11,11 +11,11 @@ module attributes { torch.debug_module_name = "MLP" } {
%1 = hls.dse.param @template1 <template> candidates [f32] : !hls.type
%2 = hls.dse.param @template2 <template> candidates [index] : !hls.type
%3 = hls.dse.param @template3 <template> candidates [4 : index] : index
%4 = hls.uip.port @para1 <param> type %2 sizes() #map : () -> !hls.port
%5 = hls.uip.port @para2 <param> type %2 sizes() #map : () -> !hls.port
%6 = hls.uip.port @input1 <input> type %1 sizes(%4, %5) #map1 : (!hls.port, !hls.port) -> !hls.port
%7 = hls.uip.port @input2 <input> type %1 sizes(%4, %5) #map1 : (!hls.port, !hls.port) -> !hls.port
%8 = hls.uip.port @output1 <output> type %1 sizes(%4, %5) #map1 : (!hls.port, !hls.port) -> !hls.port
%4 = hls.uip.port @para1 <param> type %2 sizes() symbol_ref() () #map : () -> !hls.port
%5 = hls.uip.port @para2 <param> type %2 sizes() symbol_ref() () #map : () -> !hls.port
%6 = hls.uip.port @input1 <input> type %1 sizes(%4, %5) symbol_ref() () #map1 : (!hls.port, !hls.port) -> !hls.port
%7 = hls.uip.port @input2 <input> type %1 sizes(%4, %5) symbol_ref() () #map1 : (!hls.port, !hls.port) -> !hls.port
%8 = hls.uip.port @output1 <output> type %1 sizes(%4, %5) symbol_ref() () #map1 : (!hls.port, !hls.port) -> !hls.port
hls.uip.semantics<%1, %2, %3> (%4, %5, %6, %7, %8) [2 : index, 3 : index, 4 : index] : <!hls.type, !hls.type, index> (!hls.port, !hls.port, !hls.port, !hls.port, !hls.port) {
^bb0(%arg0: tensor<?x?xf32>, %arg1: tensor<?x?xf32>, %arg2: tensor<?x?xf32>):
%9 = linalg.generic {indexing_maps = [#map1, #map1], iterator_types = ["parallel", "parallel"]} ins(%arg0 : tensor<?x?xf32>) outs(%arg1 : tensor<?x?xf32>) {
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