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Pull requests: Xilinx/ACCL

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Pull requests list

CYT V2 integration without card memory
#212 opened Aug 16, 2025 by jolandaoertli • Draft
CYT V2 integration
#211 opened Aug 16, 2025 by jolandaoertli Loading…
Configurable eager buffers
#210 opened Aug 16, 2025 by jolandaoertli Loading…
Fix incorrect offsets and size of Eager RX Buffer regs
#209 opened Jun 20, 2025 by bo3z • Draft
1
Accl cyt v2
#205 opened Oct 2, 2024 by zhenhaohe Loading…
Pytorch ddp
#204 opened Sep 29, 2024 by lawirz Loading…
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