Add cache implementation to compute cores

[Yellown42]

TL;DR

Adds a simple, educational direct-mapped L1 cache between the LSU and memory controller.
Reduces memory traffic for repeated accesses while keeping the design minimal and easy to understand.
Includes a test demonstrating cache hits vs misses.

Implementation Details

New Files

• src/cache.sv: Direct-mapped cache module (64 cache lines, write-through policy)
• src/lsu_cached.sv: Cache-enabled LSU that wraps the cache module
• test/test_cache.py: Test demonstrating cache effectiveness

Modified Files

• src/core.sv: Updated to use lsu_cached instead of lsu
• Makefile: Updated to compile cache modules

Architecture

• Direct-mapped cache: Each memory address maps to exactly one cache line
• 64 cache lines: Sufficient for demonstrating cache benefits
• Write-through policy: Writes update both cache and memory for simplicity
• Per-thread caches: Each thread has its own cache instance

Design Decisions

1. Direct-mapped: Simplest cache design, easy to understand for educational purposes
2. Write-through: Keeps cache and memory consistent without complex coherency protocols
3. Small size (64 lines): Sufficient for tiny-gpu's demonstration scale
4. Per-thread caches: Avoids cache coherency issues between threads

Testing

Run the cache test:

make test_cache

The test verifies:

• Correct data output (each thread outputs 30 = 10+10+10)
• Cache functionality (repeated reads of same address)
• Compatibility with existing tests (test_matadd, test_matmul)

Backward Compatibility

To use the original non-cached LSU, simply change lsu_cached back to lsu in src/core.sv.

Future Enhancements

Possible extensions to this implementation:

• Set-associative cache (reduce conflicts)
• Write-back policy (reduce write traffic)
• Cache statistics counters for performance analysis
• Shared L2 cache across cores
• Cache coherency protocols for multi-core scenarios