5-Stage Pipelined RISC Processor in Verilog

This project implements a basic 5-stage pipelined RISC processor that supports the following instructions:

• ADD
• SUBI
• LW (Load Word)
• OR
• NOR

📌 Features

• 5-stage pipeline: IF, ID, EX, MEM, WB
• Data forwarding unit
• Hazard detection unit
• Verilog HDL implementation
• Testbench for simulation

📂 File Structure

• top.v – Top module
• control.v, datapath.v, hazard_unit.v – Functional units

✅ Tools Used

• Verilog HDL
• Vivado for simulation

🧠 Learning Outcomes

• CPU design pipeline stages
• Instruction decoding and execution
• Managing data hazards with forwarding and stalls