mini_cpu

A 32-bit classic five-stage pipelined processor core designed using Verilog HDL, based on the RV32I instruction set. This is an implementation of a RISC-V 32-bit five-stage pipelined CPU, developed as a learning project after studying computer architecture courses.

中文版 README

Features

• Based on RISC-V RV32I instruction set
• Classic five-stage pipeline architecture
• Implemented in Verilog HDL
• Simulation and testing support

Build and Run

Compile Assembly Test Program

make asm

Run CPU Simulation

make cpu

View Simulation Waveforms

make wave

Clean Temporary Files

make clean

Project Structure

• rtl/ - Verilog source code (CPU core modules)
• sim/ - Simulation related files
• tb/ - Testbench files
• tmp/ - Temporary files directory

Dependencies

• RISC-V Toolchain (riscv64-linux-gnu)
• Icarus Verilog (iverilog)
• GTKWave (waveform viewer)
• Python3

Reference

Computer Architecture Course