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Add RISC-V architecture support #1

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12 changes: 11 additions & 1 deletion CMakeLists.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -36,8 +36,11 @@ if (ARCH STREQUAL INTEL)
elseif(ARCH STREQUAL AMD)
message(STATUS "Compiling for AMD processor.")
set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -DAMD")
elseif(ARCH STREQUAL RISCV)
message(STATUS "Compiling for RISC-V processor.")
set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -DRISCV")
else()
message(WARNING "Illegal or missing value for target processor. Set '-DARCH=[INTEL|AMD]'. Defaulting to INTEL.")
message(WARNING "Illegal or missing value for target processor. Set '-DARCH=[INTEL|AMD|RISCV]'. Defaulting to INTEL.")
set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -DINTEL")
endif()

Expand All @@ -62,5 +65,12 @@ add_executable(osiris
# dependencies
find_package(OpenSSL REQUIRED)
target_link_libraries(osiris OpenSSL::Crypto)

# RISC-V needs Capstone 5+ for RISC-V disassembly support
# Use LD_LIBRARY_PATH=/usr/local/lib at runtime to load the correct version
if (ARCH STREQUAL RISCV)
target_include_directories(osiris PRIVATE /usr/local/include)
endif()
target_link_libraries(osiris capstone)

target_link_libraries(osiris stdc++fs) # GCC version < 9 needs this to support c++ filesystem lib
12 changes: 8 additions & 4 deletions README.md
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Expand Up @@ -5,7 +5,7 @@ This repository contains the implementation of the Osiris framework discussed
in the research paper "Osiris: Automated Discovery of Microarchitectural Side Channels" (USENIX Security'21). You can find the paper at the [USENIX website](https://www.usenix.org/system/files/sec21-weber.pdf).

The framework is developed to find microarchitectural side channels in an automated manner.
Currently the implementation supports only x86 processors.
The implementation supports x86 (Intel/AMD) and RISC-V processors.

## Supported Platforms
Osiris is developed and tested on Arch Linux and Ubuntu.
Expand All @@ -24,9 +24,10 @@ Hence, we expect Osiris to work on other Linux distributions as well but we did
- Arch-Linux-package: `cmake`
- Ubuntu-package: `cmake`

#### Capstone
- Arch-Linux-package: `capstone`
#### Capstone
- Arch-Linux-package: `capstone`
- Ubuntu-packages: `libcapstone-dev, libcapstone3`
- RISC-V: Requires Capstone 5+ (build from source: https://github.com/capstone-engine/capstone)

#### OpenSSL
- Arch-Linux-package: `openssl`
Expand All @@ -47,8 +48,11 @@ On Arch-Linux:
pip install pwntools --user
```

#### RISC-V Cross-Compiler (RISC-V only, for generating instructions)
- `riscv64-elf-gcc` toolchain (provides `riscv64-elf-as`)

## Building
Just install all listed dependencies and execute `./build.sh INTEL` or `./build.sh AMD` for Intel and AMD processors, respectively.
Just install all listed dependencies and execute `./build.sh INTEL`, `./build.sh AMD`, or `./build.sh RISCV` for Intel, AMD, and RISC-V processors, respectively.

## Noise Reduction
To get precise results Osiris relies on the operating system to reduce the noise of its
Expand Down
2 changes: 2 additions & 0 deletions riscv-instructions/fetch-riscv-opcodes.sh
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@@ -0,0 +1,2 @@
#! /bin/sh
git clone https://github.com/riscv/riscv-opcodes.git riscv-opcodes
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