A layout verification tool, dedicated to analog and mixed-signals (AMS) integrated circuits (ICs), enabling visual inspection of electrical characteristics of each layout's nets.
This project aims to offer integrated circuit (IC) designers an open-source tool that allows for the visual debugging of the IC layout. The tool primarily allows for checking if the resistance and current density of the layout's nets are within the expected range - settled by the designer itself according to the circuit's specifications. This is the second version of the backbone of this tool, developed in sequence of my master thesis dissertation [1], and was also summarized in an article published in the 22' edition of IEEE's International Symposium on Circuits and Systems (ISCAS 2022) [2].
The following open source packages are used in this project:
The tool was primarily developed and tested on Unix systems (Linux and MacOS). As such, this section presents, for now, installation steps for Unix-based systems. Windows installation steps will be added afterwards.
Using Git, you can clone this repository by running the following command:git clone https://github.com/das-dias/reds.git
The tool can then be installed by running the installation script that is present inside the repository's root folder:
cd reds-master
sh install.sh
If you don't have Git installed in your machine, you can directly download this repository zip file and extract the respective root folder. The repo can be downloaded here.
After downloading and extracting the root folder inside the downloaded zip, change into the root dir of the tool and run the installation script:
unzip reds-master.zip
...
cd reds-master
sh install.sh
Note:
Python's preferred package manager Poetry is installed before proceeding with the installation of the tool's dependencies. Poetry is used to manage the tool's dependencies and virtual environment, allowing for a greater flexibility towards the version control of the tool.
Understanding the flow of the tool is an important step towards a better understanding of the tool's usage. The following figure presents the general flow of the tool.
The tool saves in its configuration json file the base paths for the Technology Rules and GDS Table files. These files are essential to interpret the information that gets parsed from the Layout Mask File by the user.
After the layout of the target integrated circuit for analysis gets imported, its metal interconnect Nets are extracted. Parasitic resistance extraction will occur in one of the extracted Nets, and the target Net will be selected by the user using the console interface.
After selecting the target Net for analysis, every metal interconnect polygon will be fragmented into a mesh of square polygons - each of them interpreted as a node belonging to a specific GDSII layer.
The user will then select the input node from which resistance will be extracted with the aid of a graphical user interface (GUI). This GUI was heavily inspired by Lucas Heitzmann's gdspy::LayoutViewer.
After resistance extraction is performed, extensively exploiting and using methods discussed in [3 - 5] for the computation of resistance between nodes belonging to a given graph topology, the final results are shown to the user once again using the dedicated GUI for showing GDSII geometry information and a report is produced to the console in text format.
A shell script is setup during the installation of the tool. The shell script allows for an easier way of using the tool through the terminal - semantic-wise.
The following shell call can be used to run the tool:
./redssh
Equivalent to:
./redssh -h
The following console output will be displayed:
This section presents an example usage of the tool to perform extraction, back-annotation and visualization of the parasitic resistance throughout a metal interconnect Net. The final visual result is directly related to IR-Drop observed throughout the Net. The results shown can help layout engineers to identify potential issues in the thickness or width of the designed metal interconnects - that inherently will lead to an excessive IR-Drop caused by an higher-than-expectable parasitic resistance of the Net.
The first step towards observing the back-annotated parasitic resistance of the net is to parse to the tool:
-
The layout mask file of the target IC
-
The name of the target Net (belonging to the parsed IC)
-
The output directory location to save the results
To do so, one can run the following example command in the terminal:
./redssh [-rpex / -cda] -l <LAYOUT_FILEPATH> -n <NET_NAME> -o <OUTPUT_DIR>
Notice that the tool is prepared to perform two types of inspections on the target IC: parasitic resistance extraction (for IR-Drop inspection) and current density analysis (for Electormigration inspection). As such the mutually exclusive flags -rpex and -cda , respectively, can be used to select the desired inspection type.
The following example shows the usage of the -rpex flag.
The tool then starts its execution chain, producing the following example console output:
A GUI then pops up to ask the user to select the square polygon that will be used as the input node for the extraction. The user can select the input node by double-clicking on the desired polygon with the left mouse-button. The following example shows the GUI:
The execution chain then proceeds to perform the extraction of the parasitic resistance of the target Net, using the selected node as the starting point. The results are then back-annotated on the layout mask file. The following example shows the final visual result for the concrete example given:
Note:
A limited number of colours is being used to create the colour palette associated with each resistance value, and therefore the output seems a bit blocky, and with a very high contrast between adjacent colours. This is due to the low discretization level, and can be changed in the configurations of the tool.
Finally, a report summarizing the run is produced to the console. The following example depicts an example of a produced report:
The analysis and observation of the current density throughout each section of the metal interconnects allows the layout engineer to detect electromigration problems associated with the designed IC layout.
The detection and resolution of such electromigration problems will allow the engineer to extend the expected time-of-life of the IC to its maximum, thus providing for a more reliable and robust IC design.
This functionality is still under development.
Coming soon...
If you have any questions or suggestions, please feel free to contact me through my institutional e-mail or through my personal e-mail. I am a PhD student in Electrical and Computer Engineering at NOVA University of Lisbon, being also enrolled in a scholarship at TU-Delft, and therefore I am not able to dedicate the time I would like to this project. I am usually quick to respond to any issues or pull requests, but please be patient if I take a while to get back to you.
If you want to contribute to the project, please feel free to fork the repository and submit a pull request. After a review and the approval of the test units, I will be more than happy to merge your changes into the main branch.
The project is still under development, and therefore any contribution is more than welcome.
[2] D. Dias,J. Goes and T. Costa, "A Parasitic ResistanceExtraction Tool Leveraged by Image Processing", 2022 IEEE International Symposium on Circuits and Systems (ISCAS), 2022, pp. 1585-1589, doi:10.1109/ISCAS48785.2022.9937879.
[3] Klein, D.J., Randić, M., "Resistance distance". J Math Chem 12, 81–95 (1993).
[4] Wolfram MathWorld, "Resistance Distance".
[5] Vos, Vaya, "Methods for determining the effective resistance", Universiteit Leiden, December 20, 2016.