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Verilog: test for gate instantiation with multiple instances #1495

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tautschnig merged 1 commit into from
Dec 19, 2025
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Verilog: test for gate instantiation with multiple instances #1495

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8 changes: 8 additions & 0 deletions regression/verilog/primitive_gates/multiple_instances1.desc
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CORE
multiple_instances1.sv

^EXIT=0$
^SIGNAL=0$
--
^warning: ignoring
--
10 changes: 10 additions & 0 deletions regression/verilog/primitive_gates/multiple_instances1.sv
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module main;

wire w1, w2;

and a1(w1, 1, 1), a2(w2, 1, 0);

initial assert(w1==1);
initial assert(w2==0);

endmodule
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