With this project we extend the existing monte carlo framework of the Vitis Quantitative Finance Library [3] and introduce a new and reusable path pricer for computing the replication error of a delta-hedging strategy in HLS and with Vitis. The implemented delta-hedging strategy follows Kamal’s 1998 research note [2]. The FPGA implementation is tested and validated against the CPU version built with QuantLib [4], the open-source library for quantitative finance. The performance of our implementation with the Vitis libraries on an Alveo U280 is compared to the QuantLib build run on an Intel Xeon Platinum 8260M.
Further investigating the Vitis open-source libraries we showcase our approach with the Greek calculators in the presented path pricer implementation and highlight peculiarities for using the library’s existing components in this regard.
To install this repository
git clone https://github.com/markxio/delta-hedging.git
cd delta-hedging
To build this repository for Alveo U280:
mkdir bin
make host
make device TARGET=hw DEVICE=xilinx_u280_xdma_201920_3
To compile the CPU reference code, go to src/cpu_total and run ./compile.sh. This initialises the git submodule for Quantuccia and compiles the reference code. Run the binary with ./DiscreteHedgingQuantuccia
To run the project:
cd bin
./host ./krnl_scenario.hw.xclbin
SAMP_NUM: overall number of samples/pathsSAMP_PER_SIM: number of samples per simulationMAX_SAMPLE: maximum number of samplesDT_USED: data type to be used, e.g. doubleMCM_NM: number of monte carlo modules in parallel (affects latency and resource utilization)
Returns the kernel result i.e. the computed replication error (Profit & Loss)
Kernel result
P&L: 0.000101
Execution complete, total runtime : 30.327 ms, (0.161 ms xfer on, 29.951 ms execute, 0.215 ms xfer off)